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AD9627-11 Datasheet(PDF) 5 Page - Analog Devices |
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AD9627-11 Datasheet(HTML) 5 Page - Analog Devices |
5 / 72 page AD9627-11 Rev. B | Page 5 of 72 SPECIFICATIONS ADC DC SPECIFICATIONS—AD9627-11-105/AD9627-11-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted. Table 1. Parameter Temperature AD9627-11-105 AD9627-11-150 Unit Min Typ Max Min Typ Max RESOLUTION Full 11 11 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±0.3 ±0.7 ±0.2 ±0.6 % FSR Gain Error Full −3.6 −2.2 −1.0 −4.3 −3.0 −1.7 % FSR Differential Nonlinearity (DNL)1 Full ±0.3 ±0.4 LSB 25°C ±0.1 ±0.1 LSB Integral Nonlinearity (INL)1 Full ±0.5 ±0.7 LSB 25°C ±0.2 ±0.3 LSB MATCHING CHARACTERISTIC Offset Error 25°C ±0.3 ±0.7 ±0.2 ±0.7 % FSR Gain Error 25°C ±0.2 ±0.75 ±0.2 ±0.7 % FSR TEMPERATURE DRIFT Offset Error Full ±15 ±15 ppm/°C Gain Error Full ±95 ±95 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Full ±5 ±16 ±5 ±16 mV Load Regulation @ 1.0 mA 25°C 7 7 mV INPUT REFERRED NOISE VREF = 1.0 V 25°C 0.15 0.15 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 V p-p Input Capacitance2 Full 8 8 pF VREF INPUT RESISTANCE Full 6 6 kΩ POWER SUPPLIES Supply Voltage AVDD, DVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD (CMOS Mode) Full 1.7 3.3 3.6 1.7 3.3 3.6 V DRVDD (LVDS Mode) Full 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Current IAVDD1, 3 Full 310 365 419 495 mA IDVDD1, 3 Full 34 50 mA IDRVDD1 (3.3 V CMOS) Full 34 42 mA IDRVDD1 (1.8 V CMOS) Full 16 29 mA IDRVDD1 (1.8 V LVDS) Full 44 46 mA POWER CONSUMPTION DC Input Full 600 650 820 890 mW Sine Wave Input1 (DRVDD = 1.8 V) Full 645 895 mW Sine Wave Input1 (DRVDD = 3.3 V) Full 730 1000 mW Standby Power4 Full 68 77 mW Power-Down Power Full 2.5 6 2.5 6 mW 1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure. 3 The maximum limit applies to the combination of IAVDD and IDVDD currents. 4 Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND). |
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