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ISL5416 Datasheet(PDF) 7 Page - Intersil Corporation |
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ISL5416 Datasheet(HTML) 7 Page - Intersil Corporation |
7 / 71 page 7 Functional Description The ISL5416 is a four channel digital receiver integrated circuit offering exceptional dynamic range and flexibility. Each of the four channels consists of a front-end NCO, digital mixer, CIC-filter, two FIR filters, AGC, Interpolation Half Band Filter and Re-sampling Filter. The parameters for the four channels are independently programmable. There are four 17-bit parallel data input busses (Ain(16:0), Bin(16:0), Cin(16:0) and Din(16:0)). The ISL5416 supports both fixed and floating point parallel data input modes. The floating point modes support gain ranging A/D converters or A/D converter and RF/IF Attenuators or VGAs. Gated or interpolated data input modes are supported. Each input can be connected to any or all of the internal signal processing channels, Channels 0, 1, 2 and 3. The four channels share a common processing clock (CLKC). Four input clocks are provided to allow for clock skew between input sources. Each input has a Range Control circuits to monitor the signal level on the parallel data busses and to control the gain prior to the A/D converters. A 16-bit bus (Eout(15:0)) is provided to control the external VGA/RF Attenuators. Each front end NCO/digital mixer/CIC filter section includes a quadrature numerically controlled oscillator (NCO), digital mixer, barrel shifter and a cascaded-integrator-comb filter (CIC). The NCO has a 32-bit frequency control word. The SFDR of the NCO is >110dB. The barrel shifter provides a gain of between 2-45 and 4 to compensate for the gain in the CIC. The CIC filter order is programmable from 1 to 5 and the CIC decimation factor can be programmed from 2 to 512 for 5th order, 2048 for 4th order, 32768 for 3rd order, or 65536 for 1st or 2nd order filters. The CIC filter can also be bypassed. Each channel back end section includes two FIR filters, an AGC, Interpolation Half Band Filter and Resampler. The first FIR filter can have up to 32 taps and the second can have up to 64 taps. The 32-tap filter calculates 4 taps per clock, while the 64-tap filter calculates 8 taps per clock. The coefficients for the programmable digital filters are 20 bits wide. Each FIR filter can be bypassed. The AGC section can provide up to 96dB of either fixed or automatic gain control. For automatic gain control, two settling modes and two sets of loop gains are provided. Separate attack and decay slew rates are provided for each loop gain. Programmable limits allow the user to specify a gain range less than 96dB. A fixed coefficient interpolate-by-2 Half Band Filter and a non-integer resampling filter follow the AGC. Coefficients for the resampling filter are provided in ROM. Four 16-bit parallel data outputs (Aout(15:0), Bout(15:0), Cout(15:0) and Dout(15:0)) are provided. The output of each channel can be routed to any of the output buses. Outputs from more than one channel can be multiplexed through a common output if the channels are synchronized. Dout(15:0)) can alternately be used as four serial output pairs. A common output clock (CLKO1) is used for the parallel output buses. A second clock output pin (CLKO2/INTRPT) is provided to simplify board routing or to allow a complementary output clocks. The ISL5416 is programmed through a 16-bit microprocessor interface. The output data can also be read via the microprocessor interface. The ISL5416 is specified to operate to a maximum clock rate of 95 MSPS over the industrial temperature range (-40oC to 85oC). The I/O power supply voltage range is 3.3V ± 0.165V while the core power supply voltage is 1.8V ± 0.09V. Input Select/Format Block CLOCKING The channel processing and output timing is clocked with the rising edge of CLKC. Each input bus can be clocked with the rising or falling edge of its own clock or with the rising or falling edge of CLKC. The frequency of all the clocks must be the same, but providing separate clocks allows the inputs from multiple A/D converters to have a small amount of skew. INPUT FORMAT The inputs can be fixed point or floating point with mantissa/exponents sizes of 14/3, 15/2, or 16/1. The exponent inputs are added to the exponent from the internal range control circuits, so if the range control circuits are used, the exponent pins are typically grounded and/or disabled via software in IWA = 0*10h, bit 3. The input format may be twos complement or offset binary format in either fixed or floating point modes (IWA = 0*00h). GATED/INTERPOLATED MODES For input sample rates at sub-multiples of the clock rate, gated and interpolated input modes are provided. Each input channel has an input enable (ENIx, x = A, B, C or D). In the gated mode, one input sample is processed per clock that the ENIx signal is asserted (low). Processing is disabled when ENIx is high. The ENIx signal is pipelined through the part to minimize delay (latency). In the interpolated mode, the input is zeroed when the ENIx signal is high, but processing inside the part continues. This mode inserts zeros between the data samples, interpolating the input data stream up to the clock rate. The spacing between ENIx signals must be constant in the interpolated mode. MULTIPLEXED INPUT MODE Each input section can select one channel from a multiplexed data stream of up to 8 channels. The input enable is delayed by 0 to 7 clock cycles to enable a selection register. The register following the selection register is enabled by the non-delayed input enable to realign the processing of the channels. The one-clock-wide input enable must align with the data for the first channel. The desired channel is then selected by programming the delay. A delay of zero selects the first channel, a delay of 1 selects the second, etc. Each input section selects only one channel of the multiplexed stream, so a separate input bus must be used for each channel of the multiplexed data stream. ISL5416 |
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Descripción similar - ISL5416 |
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