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ISL6121HIBZA Datasheet(PDF) 8 Page - Intersil Corporation |
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ISL6121HIBZA Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 16 page 8 FN9005.4 June 10, 2005 Using the ISL612XSEQEVAL1 Platform The ISL612XSEQEVAL1 platform is the primary evaluation board for this family. The board has 2 complete, separate and electrically identical circuits, see Figure 15 for schematic and Figure 16 for a photo. In the top right hand corner of the board is a SMD layout with a ISL6123 illustrating the full functionality and small implementation size for an application having the highest component count. The majority of the board is given over to a socket and discrete through-hole components circuit for ease of evaluation flexibility through IC variant swapping and modification of UVLO levels and sequencing order by passive component substitution. The board is shipped with the ISL6123 installed in both locations and with two each of the other released variant types loose packed. As this sequencer family has a common function pinout there are no major modifications to the board necessary to evaluate the other ICs. The ISL6125 due to its having open drain outputs can be evaluated on the ISL612XSEQEVAL1 with a minor modification or on the ISL613XSUPEREVAL2 evaluation platform. To modify for ISL6125 evaluation, pull-up resistors must be added from the GATE outputs to a pull-up voltage of 1.5V to prevent FET turn-on or remove FETs to eliminate this voltage restriction. To the left, right and above the socket are four test point strips (TP1-TP4). These give access to the labeled IC I/O pins during evaluation. Remember that significant current or capacitive loading of particular I/O pins will affect functionality and performance. Attention to orientation and placement of variant ICs in the socket must be paid to prevent IC damage or faulty evaluation. The default configuration of the ISL612XSEQEVAL1 circuitries was built around the following design assumptions: Typical Performance Curves FIGURE 4. UVLO THRESHOLD VOLTAGE FIGURE 5. DLY CHARGE CURRENT FIGURE 6. SYSRST# LOW TO OUTPUT LATCH OFF 634 633 632 631 628 626 TEMPERATURE (°C) 627 -40 0 20 60 -20 40 80 100 630 629 VDD = 5V VDD = 1.5V -40 0 20 60 -20 40 80 100 TEMPERATURE ( °C) 1.03 1.02 0.97 0.98 0.99 1.00 1.01 1.04 DLY_OFF/ON VDD = +5V VDD = 1.5V 1 µs/DIV 5VOUT GATE SYSRST# 2V/DIV 3.3VOUT ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128 |
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