ACE25C320G

Uniform SECTOR Dual and Quad Serial Flash

VER 1.5

9

QE bit.

The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad

operation. When the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE

pin is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during

standard SPI or Dual SPI operation if the WP# or HOLD# pins are tied directly to the power supply or

ground)

LB3/LB2/LB1 bit.

The LB bit is a non-volatile One Time Program (OTP) bit in Status Register (S10) that provide the

write protect control and status to the Security Registers. The default state of LB is 0, the security

registers are unlocked. LB can be set to 1 individually using the Write Register instruction. LB is One

Time Programmable, once it’s set to 1, the Security Registers will become read-only permanently.

LB0 is reserved, LB3/2/1 for Security Registers 3:1.

CMP bit

The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the

SEC-BP0 bits to provide more flexibility for the array protection. Please see the Status registers

Memory Protection table for details. The default setting is CMP=0.

SUS bit

The SUS bit is a read only bit in the status register (S15 ) that is set to 1 after executing an

Erase/Program Suspend (75H) command. The SUS bit is cleared to 0 by Erase/Program Resume

(7AH) command as well as a power-down, power-up cycle.

Commands Description

All commands, addresses and data are shifted in and out of the device, beginning with the most

significant bit on the first rising edge of SCLK after CS# is driven low. Then, the one-byte command

code must be shifted in to the device, most significant bit first on SI, each bit being latched on the

rising edges of SCLK.

See Table2, every command sequence starts with a one-byte command code. Depending on the

command, this might be followed by address bytes, or by data bytes, or by both or none. CS# must be

driven high after the last bit of the command sequence has been shifted in. For the command of Read,

Fast Read, Read Status Register or Release from Deep Power-Down, and Read Device ID, the

shifted-in command sequence is followed by a data-out sequence. CS# can be driven high after any

bit of the data-out sequence is being shifted out.

For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register,

Write Enable, Write Disable or Deep Power-Down command, CS# must be driven high exactly at a

byte boundary, otherwise the command is rejected, and is not executed. That is CS# must driven high

when the number of clock pulses after CS# being driven low is an exact multiple of eight. For Page

Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset.