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PD16707A Datasheet(PDF) 11 Page - Renesas Technology Corp |
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PD16707A Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 15 page  Data Sheet S16563EJ1V0DS 9 µ PD16707A Switching Characteristics (TA = –20 to +75 °C, VDD1 = 2.3 to 3.6 V, VDD2 = 20 V, VEE = –5 V, VSS = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit Cascade Output Delay Time tPHL1 CL = 20 pF, 500 ns tPLH1 CLKR (CLKL) → STVL (STVR) 500 ns tPHL2 500 ns tPLH2 CL = 300 pF, CLKR (CLKL) → On 500 ns tPHL3 500 ns Driver Output Delay Time tPLH3 CL = 300 pF, OER (OEL) → On 500 ns Output Rise Time tTLH CL = 300 pF 800 ns Output Fall Time tTHL 800 ns Input Capacitance CI TA = 25 °C 15 pF Timing Requirements (TA = −20 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 20 V, VEE = −5 V, VSS = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit Clock Pulse High Width PWCLK(H) 500 ns Clock Pulse Low Width PWCLK(L) 500 ns Enable Pulse Width PWOE 1000 ns Data Setup Time tSETUP STVR (STVL) ↑→ CLKR, CLKL↑ 200 ns Data Hold Time tHOLD CLKR, CLKL ↑→ STVR (STVL) ↓ 200 ns Remark Unless otherwise specified, the input level is defined to be VIH = 0.8 VDD1, VIL = 0.2 VDD1. Caution Keep the time and fall time of the logic input to tr = tf = 20 ns (10 to 90% of the rated values). ★ |
Número de pieza similar - PD16707A_15 |
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Descripción similar - PD16707A_15 |
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