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Improved, Dual, High-Speed Analog Switches 6 _______________________________________________________________________________________ ______________________________________________Timing Diagrams/Test Circuits 50% tOFF tr < 20ns tf < 20ns VOUT VOUT tON 0.9 x VOUT 0.9 x VOUT +3V 0V 0V LOGIC INPUT SWITCH OUTPUT LOGIC INPUT WAVEFORM IS INVERTED FOR SWITCHES THAT HAVE THE OPPOSITE LOGIC SENSE CONTROL. +5V +15V VOUT RL = 1000Ω CL = 35pF -15V REPEAT TEST FOR IN2 AND S2 0V GND LOGIC INPUT VD = +10V (for tON) VD = -10V (for tOFF) FOR LOAD CONDITIONS, SEE Electrical Characteristics. CL INCLUDES FIXTURE AND STRAY CAPACITANCE. VOUT = VD RL RL + rDS(ON) V+ VL V- D IN S ( ) DG401 DG403 DG405 VGEN GND CL 10nF VOUT 0V -15V V- VL V+ RGEN VOUT IN ON OFF ON ∆VOUT Q = ( ∆VOUT) (CL) +5V +15V SD DG401 DG403 DG405 50% VOUT1 VOUT2 0.9 x VOUT +3V 0V 0V LOGIC INPUT SWITCH OUTPUT 1 SWITCH OUTPUT 2 +5V VL +15V V+ V- -15V CL INCLUDES FIXTURE AND STRAY CAPACITANCE. 0V GND LOGIC INPUT 0V 0.9 x VOUT tD tD IN RL2 CL2 VOUT2 RL1 VOUT1 CL1 RL = 1000Ω CL = 35pF D D S S +10V +10V DG401 DG403 DG405 Figure 2. Switching Time Figure 4. Charge Injection Figure 3. Break-Before-Make Interval |
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