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9ZXL1230 Datasheet(PDF) 4 Page - Integrated Device Technology |
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9ZXL1230 Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 18 page 9ZXL1230 12-OUTPUT LOW POWER DIFFERENTIAL BUFFER FOR PCIE GEN3 AND QPI IDT® 12-OUTPUT LOW POWER DIFFERENTIAL BUFFER FOR PCIE GEN3 AND QPI 4 9ZXL1230 REV B 041112 Pin Descriptions PIN # PIN NA ME TYPE DESCRIPTION 1 GNDA PWR Ground pin for the PLL core. 2 NC N/A N o Connection. 3 100M_133M# IN 3.3V Input to select operating frequency See Functionality Table for Definition 4 HIBW_BYPM_LOBW# IN Trilevel input to select High BW, Bypass or Low BW mode. See PLL Operating Mode Table for D etails. 5CKPWRGD_PD# IN N otifies device to sample latched inputs and start up on first high assertion, or exit Power Down Mode on subsequent assertions. Low enters Power Down Mode. 6 GND PWR Ground pin. 7VDDR PWR 3.3V power for differential input clock (receiver). This VDD should be treated as an analog power rail and filtered appropriately. 8 DIF_IN IN 0.7 V Differential TRUE input 9 DIF_IN# IN 0.7 V Differential Complementary Input 10 SMB_A0_tri IN SMBus address bit. This is a tri-level input that w orks in conjunction with the SMB_A1 to decode 1 of 9 SMBus Addresses. 11 SMBDAT I/O D ata pin of SMBUS circuitry, 5V tolerant 12 SMBCLK IN C lock pin of SMBU S circuitry, 5V tolerant 13 SMB_A1_tri IN SMBus address bit. This is a tri-level input that w orks in conjunction with the SMB_A0 to decode 1 of 9 SMBus Addresses. 14 DFB_OUT_NC# OUT C omplementary half of differential feedback output, provides feedback signal to the PLL for synchronization w ith input clock to eliminate phase error. This pin should NOT be connected on the circuit board, the feedback is internal to the package. 15 DFB_OUT_NC OUT True half of differential feedback output, provides feedback signal to the PLL for synchronization with the input clock to eliminate phase error. This pin should NOT be connected on the circuit board, the feedback is internal to the package. 16 DIF_0 OUT 0.7V differential true clock output 17 DIF_0# OUT 0.7V differential Complementary clock output 18 DIF_1 OUT 0.7V differential true clock output 19 DIF_1# OUT 0.7V differential Complementary clock output 20 GND PWR Ground pin. 21 VDD PWR Power supply, nominal 3.3V 22 VDDIO PWR Power supply for differential outputs 23 DIF_2 OUT 0.7V differential true clock output 24 DIF_2# OUT 0.7V differential Complementary clock output 25 OE2# IN Active low input for enabling DIF pair 2. 1 =disable outputs, 0 = enable outputs 26 DIF_3 OUT 0.7V differential true clock output 27 DIF_3# OUT 0.7V differential Complementary clock output 28 VDDIO PWR Power supply for differential outputs 29 GND PWR Ground pin. 30 DIF_4 OUT 0.7V differential true clock output 31 DIF_4# OUT 0.7V differential Complementary clock output |
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