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STC5423 Datasheet(PDF) 6 Page - Connor-Winfield Corporation |
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STC5423 Datasheet(HTML) 6 Page - Connor-Winfield Corporation |
6 / 60 page Page 6 of 60 TM114 Rev:1.4 Date: October 24, 2011 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice STC5423 Synchronous Clock for SETS Data sheet STC5423 Pin Description All I/O is LVCMOS, except for CLK1 and CLK2, which are LVPECL/LVDS. Table 1: Pin Description Pin Name Pin # I/O Description AVCC 6,19, 3.3V analog power input AGND 5, 20, Analog ground VCC 12, 13, 16, 33, 39, 50, 61, 85, 86, 91 3.3V power input GND 1, 11, 14, 15, 32, 38, 49, 62, 84, 87, 92 Digital ground TRST 2 I JTAG boundary scan reset, active low TCK 9 I JTAG boundary scan clock TMS 7 I JTAG boundary scan mode selection TDI 23 I JTAG boundary scan data input TDO 21 O JTAG boundary scan data output RST 74 I Active low to reset the chip MCLK 10 I Master clock input (TCXO or OCXO) EVENT_INTR 8 O Event interrupt REF1 46 I Reference input 1 REF2 47 I Reference input 2 CLK1_P 34 O Clock output CLK1 positive. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G1. LVPECL or LVDS CLK1_N 35 O Clock output CLK1 negative. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G1. LVPECL or LVDS CLK2_P 36 O Clock output CLK2 positive. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G2. LVPECL or LVDS CLK2_N 37 O Clock output CLK2 negative.1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G2. LVPECL or LVDS CLK3 88 O Clock output CLK3. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G3 or Synthe- sizer GT4 (T4). LVCMOS. CLK4 89 O Clock output CLK4. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G4 or Synthe- sizer GT4 (T4). LVCMOS. CLK5 90 O Clock output CLK5. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G5 or Synthe- sizer GT4 (T4). LVCMOS. |
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