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932SQ420D Datasheet(PDF) 2 Page - Integrated Device Technology |
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932SQ420D Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 28 page 932SQ420D PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 2 932SQ420D REV J 010715 Pin Configuration - 64TSSOP Spread Spectrum Control Power Group Pin Numbers 932SQ420 Power Down Functionality SMBCLK 1 64 SMBDAT GND14 2 63 VDDCPU AVDD14 3 62 CPU3T VDD14 4 61 CPU3C vREF14_3x/TEST_SEL 5 60 CPU2T GND14 6 59 CPU2C GNDXTAL 7 58 GNDCPU X1_25 8 57 VDDCPU X2_25 9 56 CPU1T VDDXTAL10 55CPU1C GN DPCI 11 54 CPU0T VD DPCI 12 53 CPU0C PCI4_2x 13 52 GNDNS PCI3_2x 14 51 AVDD_NS_SAS PCI2_2x 15 50 NS_SAS1T PCI1_2x 16 49 NS_SAS1C PCI0_2x 17 48 NS_SAS0T GN DPCI 18 47 NS_SAS0C VD DPCI 19 46 GNDNS VDD4820 45VDDNS ^48M_2x/100M_133M# 21 44 NS_SRC1T GND4822 43NS_SRC1C GND9623 42NS_SRC0T DOT96T 24 41 NS_SRC0C DOT96C 25 40 IREF AVDD96 26 39 GNDSRC TEST_MODE 27 38 AVDD_SRC CKPWR GD#/PD 28 37 VDDSRC VDDSRC 29 36 SRC2T SRC0T 30 35 SRC2C SRC0C 31 34 SRC1T GNDSRC 32 33 SRC1C 64-TSSOP Note: Pins with ^ prefix have internal 120K pullup Pins with v prefix have internal 120K pulldown SS_Enable (B1b0) CPU, SRC & PCI 0OFF 1ON VDD GND VDD GND 57 56 3 2 14MH z PLL Analog 58 60 4 6 REF14M Output and Logic 64 61 10 7 25MH z XTAL 2, 9 1, 8 12, 19 11, 18 PCI Outputs and Logic 10 12 20 22 48MH z Output and Logic 16 13 26 23 96MH z PLL Analog, Output and Logic 19, 27 22 29, 37 32 SRC Out puts and Logic 28 29 38 39 SRC PLL Analog 35 36 45 46 Non-Spreading Differential Outputs & Logic 41 42 51 52 NS-SAS/SRC PLL Analog 47, 53 48 57,63 58 CPU Out puts and Logic MLF Description TSSOP CK PWRGD#/PD Differential Outputs Single-ended Outputs Single ended Outputs w/Latch 1HI-Z 1 Low Low 2 0 2. These outputs are Hi-Z after VDD is applied and before the first assertion of CKPWR GD #. Running 1. Hi-Z on the differential outputs w ill result in both True and Complement being low due to the termination network |
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