8T73S208A-01 DATA SHEET

2.5V, 3.3V DIFFERENTIAL LVPECL CLOCK DIVIDER AND BUFFER

2

REVISION 1 06/15/15

Pin Descriptions and Pin Characteristics

Table 1. Pin Descriptions

NOTE: Pulldown and Pullup refers to an internal input resistors. See Section, “Table 2. Pin Characteristics” values.

Table 2. Pin Characteristics

Number

Name

Type

Description

1,

32

ADR1, ADR0

Input

Pulldown

2, 7, 18, 23

Power

Negative supply pins.

3, 4

Q0, nQ0

Output

Differential output pair 0. LVPECL interface levels.

5, 6

Q1, nQ1

Output

Differential output pair 1. LVPECL interface levels.

8, 17

Power

Output supply pins.

9, 10

Q2, nQ2

Output

Differential output pair 2. LVPECL interface levels.

11, 12

Q3, nQ3

Output

Differential output pair 3. LVPECL interface levels.

13, 14

Q4, nQ4

Output

Differential output pair 4. LVPECL interface levels.

15, 16

Q5, nQ5

Output

Differential output pair 5. LVPECL interface levels.

19, 20

Q6, nQ6

Output

Differential output pair 6. LVPECL interface levels.

21, 22

Q7, nQ7

Output

Differential output pair 7. LVPECL interface levels.

24,

25

FSEL0,

FSEL1

Input

Pulldown

Frequency divider select controls. See Table 3A for function.

LVCMOS/LVTTL interface levels.

26

IN

Input

Non-inverting differential clock input. RT = 50

 termination to V

T.

27

Termination

Input

Input for termination. Both IN and nIN inputs are internally terminated 50



to this pin. See input termination information in Section, “Applications

Information”.

28

nIN

Input

Inverting differential clock input. RT = 50

 termination to V

T.

29

Power

Power supply pin.

30

SDA

I/O

Pullup

open drain.

31

SCL

Input

Pullup

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

2

pF

Input Pulldown Resistor

51

k



Input Pullup Resistor

51

k

