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ADC08D1520WGMPR Datasheet(PDF) 4 Page - Texas Instruments

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No. de pieza ADC08D1520WGMPR
Descripción Electrónicos  ADC08D1520QML Low Power, 8-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter
Download  59 Pages
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
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ADC08D1520WGMPR Datasheet(HTML) 4 Page - Texas Instruments

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GND
V
A
50k
50k
200k
8pF
GND
VA
GND
V
A
50k
50k
200k
8pF
V
A
SDATA
DDR
GND
VA
50 k:
ADC08D1520QML-SP
SNAS420O – JANUARY 2008 – REVISED MARCH 2013
www.ti.com
Pin Descriptions and Equivalent Circuits
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
Output Voltage Amplitude and Serial Interface Clock. Tie this
pin high for normal differential DCLK and data amplitude.
Ground this pin for a reduced differential output amplitude
and reduced power consumption. See The LVDS Outputs.
3
OutV / SCLK
When the extended control mode is enabled, this pin
functions as the SCLK input which clocks in the serial data.
See the approriate section for details on the extended control
mode. See THE SERIAL INTERFACE for description of the
serial interface.
A logic high on the PDQ pin puts only the Q-Channel ADC
29
PDQ
into the Power Down mode.
DCLK Edge Select, Double Data Rate Enable and Serial Data
Input. This input sets the output edge of DCLK+ at which the
output data transitions. See OutEdge and Demultiplex Control
Setting When this pin is connected to 1/2 the supply
OutEdge / DDR /
4
voltage,VA/2, DDR clocking is enabled. When the Extended
SDATA
Control Mode is enabled, this pin functions as the SDATA
input. See the appropriate section for details on the Extended
Control Mode. See THE SERIAL INTERFACE for description
of the serial interface.
DCLK Reset. When single-ended DCLK_RST is selected by
setting pin 52 logic high or to VA/2, a positive pulse on this pin
is used to reset and synchronize the DCLK outputs of multiple
DCLK_RST/DCLK
converters. See MULTIPLE ADC SYNCHRONIZATION for
15
_RST+
detailed description. When differential DCLK_RST is selected
by setting pin 52 logic low, this pin receives the positive
polarity of a differential pulse signal used to reset and
synchronize the DCLK outputs of multiple converters.
Power Down Pins. A logic high on the PD pin puts the entire
26
PD
device into the Power Down Mode.
Calibration Cycle Initiate. A minimum tCAL_L input clock cycles
logic low followed by a minimum of tCAL_H input clock cycles
30
CAL
high on this pin initiates the calibration sequence. See
Calibration for an overview of calibration and Initiating
Calibration for a description of calibration.
Full Scale Range Select, Alternate Extended Control Enable
and DCLK_RST-. This pin has two functions. It can
conditionally control the ADC full-scale voltage, or become
the negative polarity signal of a differential pair in differential
DCLK_RST Mode. If pin 52 and pin 41 are connected at logic
high, this pin can be used to set the full-scale-range. When
used as the FSR pin, a logic low on this pin sets the full-scale
14
FSR/DCLK_RST-
differential input range to a reduced VIN input level. A logic
high on this pin sets the full-scale differential input range to
Higher VIN input level. See Converter Electrical
Characteristics. When pin 52 is held at logic low, this pin acts
as the DCLK_RST- pin. When in differential DCLK_RST
Mode, there is no pin-controlled FSR and the full-scale-range
is defaulted to the higher VIN input level.
4
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