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ISL33001IRT2Z Datasheet(PDF) 8 Page - Intersil Corporation |
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ISL33001IRT2Z Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 18 page ISL33001, ISL33002, ISL33003 8 FN7560.6 July 11, 2014 Submit Document Feedback Application Information The ISL33001, ISL33002, ISL33003 ICs are 2-Wire Bidirectional Bus Buffers designed to drive heavy capacitive loads in open-drain/open-collector systems. The ISL33001, ISL33002, ISL33003 incorporate rise time accelerator circuitry that improves the rise time for systems that use a passive pull-up resistor for logic HIGH. These devices also feature hot swapping circuitry for applications that require hot insertion of boards into a host system (i.e., servers racks and I/O card modules). The ISL33001 features a logic output flag (READY) that signals the status of the buffer and an EN pin to enable or disable the buffer. The ISL33002 features two separate supply pins for voltage level shifting on the I/O pins and a logic input to disable the rise time accelerator circuitry. The ISL33003 features an EN pin and the level shifting functionality. I2C and SMBUS Compatibility The ISL33001, ISL33002, ISL33003 ICs are I2C and SMBUS compatible devices, designed to work in open-drain/open-collector bus environments. The ICs support both clock stretching and bus arbitration on the SDA and SCL pins. They are designed to operate from DC to more than 400kHz, supporting Fast Mode data rates of the I2C specification.In addition, the buffer rise time accelerators are designed to increase the capacitive drive capability of the bus. With careful choosing of components, driving a bus with the I2C specified maximum bus capacitance of 400pF at 400kHz data rate is possible. Start-Up Sequencing and Hot Swap Circuitry The ISL33001, ISL33002, ISL33003 buffers contain undervoltage lock out (UVLO) circuitry that prevents operation of the buffer until the IC receives the proper supply voltage. For VCC1 and VCC2, this voltage is approximately 1.8V on the rising edge of the supply voltage. Externally driven signals at the SDA/SCL pins are ignored until the device supply voltage is above 1.8V. This prevents communication errors on the bus until the device is properly powered up. The UVLO circuitry is also triggered on the falling edge when the supply voltage drops below 1.7V. Once the IC comes out of the UVLO state, the buffer remains disconnected until it detects a valid connection state. A valid connection state is either a BUS IDLE condition (see Figure 4) or a STOP BIT condition (a rising edge on SDA_IN when SCL_IN is high) along with the SCL_OUT and SDA_OUT pins being logic high. Note: For the ISL33001 and ISL33003 with EN pins, after coming out of UVLO, there will be an additional delay from the enable circuitry if the EN pin voltage is not rising at the same time as the supply pins (see Figure 3) before a valid connection state can be established. Coming out of UVLO but prior to a valid connection state, the SDA and SCL pins are pre-charged to 1V to allow hot insertion. Because the bus at any time can be between 0V and VCC, pre-charging the I/O pins to 1V reduces the maximum differential voltage from the buffer I/O pin and the active bus. FIGURE 10. CIRCUIT BLOCK DIAGRAM U1 U2 M1 M2 LOGIC CONTROL START-UP CIRCUITRY PRECHARGE CIRCUIT RISE TIME ACCELERATOR SDA_OUT SDA_IN VCC1 EN VCC2 ACC READY U3 U4 M3 M4 SCL_OUT SCL_IN M5 ISL33001 AND ISL33003 ISL33001 ONLY ISL33002 ONLY ISL33002 AND ISL33003 |
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