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ISL33002MSOPEVAL1Z Datasheet(PDF) 6 Page - Intersil Corporation |
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ISL33002MSOPEVAL1Z Datasheet(HTML) 6 Page - Intersil Corporation |
6 / 18 page ISL33001, ISL33002, ISL33003 6 FN7560.6 July 11, 2014 Submit Document Feedback Test Circuits and Waveforms FIGURE 3. ENABLE DELAY TIME FIGURE 4. BUS IDLE TIME FIGURE 5A. TEST CIRCUIT FIGURE 5B. MEASUREMENT POINTS FIGURE 5. INPUT TO OUTPUT OFFSET VOLTAGE FIGURE 6A. TEST CIRCUIT FIGURE 6B. MEASUREMENT POINTS FIGURE 6. OUTPUT LOW VOLTAGE VCC 0V VEN VREADY VCC 0V 0.5*VCC 0.5*VCC tDELAY1 - SDA_OUT and SCL pins connected to VCC - Enable Delay Time Measured on ISL33001 only - ISL33003 performance inferred from ISL33001 VSDA_IN 0.5*VCC tREADY-LH tDELAY2 - If tDELAY1 < tEN-LH then tDELAY2 = tEN-LH + tIDLE + tREADY-LH - If tDELAY1 > tEN-LH then tDELAY2 = tEN-LH + tREADY-LH - VSDA_IN = VSDA_OUT = VSCL_OUT = VEN = VCC VCC 0V VREADY VCC 0V 0.5VCC 0.5VCC tIDLE - EN Logic Input must be high for t > Enable Delay (tEN_LH) VSCL_IN - Bus Idle Time Measured on ISL33001 only - ISL33002 and ISL33003 performance inferred from ISL33001 prior to SCL_IN transition SCL_IN SDA_IN SCL_OUT SDA_OUT VCC1 +3.3V 0.2V 10kΩ 10kΩ 10kΩ 10kΩ GND 0.2V VIN VIN SCL_IN OR SDA_IN SCL_OUT OR SDA_OUT VO 0.2V VOS = VO - 0.2V SCL_IN SDA_IN SCL_OUT SDA_OUT VCC1 +2.7V 0V 900Ω 900Ω 900Ω GND 0V 900Ω SCL_OUT VOL VCC1 SDA_OUT VOL VCC1 |
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