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TC534CPL Datasheet(PDF) 8 Page - Microchip Technology |
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TC534CPL Datasheet(HTML) 8 Page - Microchip Technology |
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8 / 22 page  TC530/TC534 DS21433B-page 8 © 2002 Microchip Technology Inc. 3.0 DETAILED DESCRIPTION 3.1 Dual Slope Integrating Converter The TC530/TC534 dual slope converter operates by integrating the input signal for a fixed time period, then applying an opposite polarity reference voltage while timing the period (counting clocks pulses) for the inte- grator output to cross 0V (deintegrating). The resulting count is read as conversion data. A simple mathematical expression that describes dual slope conversion is: EQUATION 3-1: EQUATION 3-2: from which: EQUATION 3-3: And therefore: EQUATION 3-4: Inspection of Equation 3-4 shows dual slope converter accuracy is unrelated to integrating resistor and capac- itor values, as long as they are stable throughout the measurement cycle. This measurement technique is inherently ratiometric (i.e., the ratio between the TINT and TDEINT times is equal to the ratio between VIN and VREF). Another inherent benefit is noise immunity. Input noise spikes are integrated, or averaged to zero, during the integration period. The integrating converter has a noise immunity with an attenuation rate of at least -20dB per decade. Interference signals with frequencies at integral multiples of the integration period are, for the most part, completely removed. For this reason, the integration period of the converter is often established to reject 50/ 60Hz line noise. The ability to reject such noise is shown by the plotofFigure 3-1. In addition to the two phases required for dual slope measurement (Integrate and De-integrate), the TC530/ TC534 performs two additional adjustments to minimize measurement error due to system offset volt- ages. The resulting four internal operations (conver- sion phases) performed each measurement cycle are: Auto Zero (AZ), Integrator Output Zero (IZ), Input Inte- grate (INT) and Reference De-integrate (DINT). The AZ and IZ phases compensate for system offset errors and the INT and DINT phases perform the actual A/D conversion. FIGURE 3-1: INTEGRATING CONVERTER NORMAL MODE REJECTION 3.2 Auto Zero Phase (AZ) This phase compensates for errors due to buffer, inte- grator and comparator offset voltages. During this phase, an internal feedback loop forces a compensat- ing error voltage on auto zero capacitor (CAZ). The duration of the AZ phase is programmable via the serial port (see Section 4.1.1, AZ and INT Phase Duration). Integrate Voltage = De-integrate Voltage 1 RINTCINT TINT 0 VIN(T)DT = ∫ 1 RINTCINT TDEINT 0 ∫ VREF (VIN) (RINT)(CINT) [ (TINT) =(V REF) ] (RINT)(CINT) [ (TDEINT) ] VIN =VREF [ ] TINT TDEINT where: VREF = Reference Voltage TINT =Integrate Time TDEINT = Reference Voltage De-integrate Time 30 20 10 0 0.1/T 1/T 10/T Input Frequency T = Measurement Period |
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