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TPS51220 Datasheet(PDF) 8 Page - Texas Instruments |
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TPS51220 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 43 page  DRVH2 VIN VREG3 EN2 DRVH1 V5SW RF EN1 PGOOD2 SKIPSEL2 CSP2 CSN2 PGOOD1 SKIPSEL1 CSP1 CSN1 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 RHBPACKAGE (TOP VIEW) TPS51220 SLVS785C – OCTOBER 2007 – REVISED JULY 2009 www.ti.com DEVICE INFORMATION PINOUT TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. DRVH1 1 High-side MOSFET gate driver outputs. Source 1.7 Ω, sink 1.0Ω, SW-node referenced floating driver. Drive O voltage corresponds to VBST to SW voltage. DRVH2 24 SW2 25 I/O High-side MOSFET gate driver returns. SW1 32 Always alive 3.3-V, 10-mA low dropout linear regulator output. Bypass to (signal) GND with more than 1- μF VREG3 22 O ceramic capacitor. Runs from VIN supply or from VREG5 when it is switched over to V5SW input. EN1 4 Channel 1 and channel 2 SMPS enable Pins. When turning on, apply greater than 0.55 V and less than 6 V, I or be floating. Connect to GND to disable. Adjustable soft-start capacitance to be attached here. EN2 21 PGOOD1 5 Power Good window comparator outputs for channel 1 and channel 2. The applied voltage should be less O than 6 V, and the recommended pull-up resistance value is from 100 k Ω to 1 MΩ. PGOOD2 20 SKIPSEL1 6 Skip mode selection pin. GND: Continuous conduction mode I VREF2: Auto skip SKIPSEL2 19 VREG3: OOA auto skip, maximum 7 skips (suitable for fsw < 400 kHz) VREG5: OOA auto skip, maximum 15 skips (suitable for equal to or greater than 400 kHz) CSP1 7 Current sense comparator inputs (+). An RC network with high quality X5R or X7R ceramic capacitor should I/O be used to extract voltage drop across DCR. 0.1 μF is a good value to start the design. See the current CSP2 18 sensing scheme section for more details. CSN1 8 Current sense comparator inputs (–). See the current sensing scheme section. Used as power supply for the I current sense circuit for 5 V or higher output voltage setting. Also, used for output discharge terminal. CSN2 17 VFB1 9 SMPS voltage feedback inputs. Connect the feedback resistors divider, and should be referred to (signal) I GND. VFB2 16 COMP1 10 Loop compensation pin for current mode (error amplifier output). Connect R (and C if required) from this pin to VREF2 for proper loop compensation with current mode operation. Ramp compensation adjustable pin for I D-CAP mode, connect R from this pin to VREF2. 10 k Ω is a good value to start the design. 6 kΩ to 20 kΩ COMP2 15 can be chosen. See the D-CAP MODE section for more details. Frequency setting pin. Connect a frequency setting resistor to (signal) GND. Connect to an external clock for RF 3 I/O synchronization. 8 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Links :TPS51220 |
Número de pieza similar - TPS51220_15 |
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Descripción similar - TPS51220_15 |
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