DEVICE INFORMATION

TPS51427A

TERMINAL FUNCTIONS

TERMINAL

NAME

NO.

I/O

DESCRIPTION

DRVH1

15

High-side N-Channel FET driver outputs. LL referenced floating drivers. The gate drive voltage is defined by the voltage across

O

VBST to LL node bootstrap capacitor.

DRVH2

26

DRVL1

18

O

Synchronous low-side MOSFET driver outputs. Ground referenced drivers. The gate drive voltage is defined by V5DRV voltage.

DRVL2

23

EN1

14

Channel enable pins. If EN1 is connected to VREF2, Channel1 starts after Channel2 reaches regulation (delay start). If EN2 is

I

connected to VREF2, Channel2 starts after Chanel1 reaches regulation.

EN2

27

LDO Enable Input. The LDO is enabled if EN_LDO is within logic high level and disabled if EN_LDO is less than the logic low

EN_LDO

4

I

level.

GND

21

I

Analog ground for both channels and LDO.

LL1

16

I/O

and input voltage monitor for on-time control circuitry.

LL2

25

Linear regulator output. The LDO regulator can provide a total of 100-mA external loads. The LDO regulates at 5 V If LDOREFIN

is connected to GND. When the LDO is set at 5 V and VSW is within a 5-V switchover threshold, the internal regulator shuts

down and the LDO output pin connects to VSW through a 0.7-

Ω switch. The LDO regulates at 3.3 V if LDOREFIN is connected

LDO

7

O

to V5FILT. When the LDO is set at 3.3 V and VSW is within a 3.3-V switchover threshold, the internal regulator shuts down and

the LDO output pin connects to VSW through a 0.7-

Ω switch. Bypass the LDO output with a minimum of 4.7-

µF ceramic

capacitance.

LDO Reference Input. Connect LDOREFIN to GND for fixed 5-V operation. Connect LDOREFIN to V5FILT for fixed 3.3-V

LDOREFIN

8

I

operation. LDOREFIN can be used to program LDO output voltage from 0.7 V to 4.5 V. LDO output is twice the voltage of

LDOREFIN. There is no switchover in adjustable mode.

Ground pin for drivers and LS synchronous FET source terminals. This pin is also the input to zero crossing comparator and

PGND

22

I

overcurrent comparator.

PGOOD1

13

Channel1/Channel2 power-good open-drain output. PGOOD1/PGOOD2 is low when the Channel1/Channel2 output voltage is

O

10% less than the normal regulation point, at onset of OVP events, or during soft start. PGOOD1/PGOOD2 is high impedance

PGOOD2

28

when the output is in regulation and the soft-start circuit has terminated. PGOOD1/PGOOD2 is low in shutdown.

Output voltage control for Channel2. Connect REFIN2 to V5FILT for fixed 3.3-V operation. Connect REFIN2 to VREF3 for fixed

REFIN2

32

I

1.05-V operation. REFIN2 can be used to program Channel2 output voltage from 0.5 V to 2.5 V.

NC

20

-

Low-noise mode control. Connect SKIPSEL to GND for Auto Skip mode operation or to V5FILT for PWM mode (fixed frequency).

SKIPSEL

29

I

Connect to VREF2 or leave floating for OOA™ mode operation.

Frequency select input. Connect to GND for 400-kHz/500-kHz operation. Connect to VREF2 (or leave open) for

TONSEL

2

I

400-kHz/300-kHz operation. Connect to V5FILT for 200-kHz/300-kHz operation (5-V/3.3-V SMPS switching frequencies,

respectively).

TRIP1

12

I

Overcurrent trip point set input. Sourcing current is 5

µA at RT with 2900 ppm/°C temperature coefficient.

TRIP2

31

Supply voltage for the low-side MOSFET driver DRVL1/DRVL2. Connect a 5-V power source to the V5DRV pin (bypass with

V5DRV

19

I

4.7-

µF MLCC capacitor to PGND if necessary).

V5FILT

3

I

5-V analog supply input.

Channel1 feedback input. Connect VFB1 to GND for fixed 5-V operation. Connect VFB1 to V5FILT for fixed 1.5-V operation.

VFB1

11

I

Connect VFB1 to a resistive voltage divider from OUT1 to GND to adjust the output from 0.7 V to 5.9 V.

VBST1

17

I

Supply input for high-side MOSFET driver (bootstrap terminal). Connect a capacitor from this pin to the respective LL terminals.

VBST2

24

Power supply input. VIN supplies power to the linear regulators. The linear regulators are powered by Channel1 if VOUT1 is set

VIN

6

I

greater than 5 V and VSW is tied to VOUT1.

VOUT1

10

O

Output connections to SMPS. These terminals serve two functions: on-time adjustment and output discharge.

VOUT2

30

VREF2

1

O

2-V reference output. Bypass to GND with a 0.1-

µF capacitor. VREF2 can source up to 50 µA for external loads.

VREF3

5

O

3.3-V reference output. VREF3 can source up to 10 mA for external loads. Bypass to GND with a 1-

µF capacitor.

VSW is the switchover source voltage for the LDO when LDOREFIN is connected to GND or V5FILT. Connect VSW to 5 V if

VSW

9

I

LDOREFIN is tied GND. Connect VSW to 3.3 V if LDOREFIN is tied to V5FILT.

Copyright © 2008, Texas Instruments Incorporated

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9

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