SN74LS192

http://onsemi.com

5

Symbol

Parameter

Limits

Unit

Test Conditions

Min

Typ

Max

Maximum Clock Frequency

25

32

MHz

17

18

26

24

ns

16

15

24

24

ns

Clock to Q

27

30

38

47

ns

PL to Q

24

25

40

40

ns

MR Input to Any Output

23

35

ns

Symbol

Parameter

Limits

Unit

Test Conditions

Min

Typ

Max

Any Pulse Width

20

ns

Data Setup Time

20

ns

Data Hold Time

5.0

ns

Recovery Time

40

ns

DEFINITIONS OF TERMS

the correct logic level to be present at the logic input prior to

the PL transition from LOW-to-HIGH in order to be

recognized and transferred to the outputs.

PL transition from LOW-to-HIGH that the logic level must be

maintained at the input in order to ensure continued

recognition. A negative HOLD TIME indicates that the

correct logic level may be released prior to the PL transition

from LOW-to-HIGH and still be recognized.

required between the end of the reset pulse and the clock

transition from LOW-to-HIGH in order to recognize and

transfer HIGH data to the Q outputs.