TMP75B

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SBOS706B – APRIL 2014 – REVISED AUGUST 2014

7.3.3.4 Slave-Mode Operations

The TMP75B can operate as a slave receiver or slave transmitter.

7.3.3.4.1

Slave Receiver Mode:

The first byte transmitted by the master is the slave address, with the R/W bit low. The TMP75B then

acknowledges reception of a valid address. The next byte transmitted by the master is the pointer register. The

TMP75B then acknowledges reception of the pointer register byte. The next byte or bytes are written to the

register addressed by the pointer register. The TMP75B acknowledges reception of each data byte. The master

can terminate data transfer by generating a start or stop condition.

7.3.3.4.2

Slave Transmitter Mode:

The first byte transmitted by the master is the slave address, with the R/W bit high. The slave acknowledges

reception of a valid slave address. The next byte is transmitted by the slave and is the most significant byte of

the register indicated by the pointer register. The master acknowledges reception of the data byte. The next byte

transmitted by the slave is the least significant byte. The master acknowledges reception of the data byte. The

master can terminate data transfer by generating a not-acknowledge bit on reception of any data byte, or by

generating a start or stop condition.

7.3.3.5 SMBus Alert Function

The TMP75B supports the SMBus alert function. When the TMP75B operates in interrupt mode (TM = 1), the

ALERT pin may be connected as an SMBus alert signal. When a master senses that an alert condition is present

on the ALERT line, the master sends an SMBus alert command (00011001) to the bus. If the ALERT pin is

active, the device acknowledges the SMBus alert command and responds by returning its slave address on the

SDA line. The eighth bit (LSB) of the slave address byte indicates whether the alert condition is caused by the

If multiple devices on the bus respond to the SMBus alert command, arbitration during the slave address portion

of the SMBus alert command determines which device clears its alert status first. If the TMP75B wins the

arbitration, its ALERT pin becomes inactive at the completion of the SMBus alert command. If the TMP75B loses

the arbitration, its ALERT pin remains active.

7.3.3.6 General Call

The TMP75B responds to a two-wire general call address (0000000) if the eighth bit is 0. The device

acknowledges the general call address and responds to commands in the second byte. If the second byte is

00000100, the TMP75B latches the status of the address pin, but does not reset. If the second byte is 00000110,

the TMP75B internal registers are reset to power-up values.

7.3.3.7 High-Speed (Hs) Mode

In order for the two-wire bus to operate at frequencies above 400 kHz, the master device must issue an SMBus

Hs-mode master code (00001xxx) as the first byte after a start condition to switch the bus to high-speed

operation. The TMP75B does not acknowledge this byte, but does switch its input filters on SDA and SCL and its

output filters on SDA to operate in Hs-mode, allowing transfers at up to 3 MHz. After the Hs-mode master code

has been issued, the master transmits a two-wire slave address to initiate a data-transfer operation. The bus

continues to operate in Hs-mode until a stop condition occurs on the bus. Upon receiving the stop condition, the

TMP75B switches the input and output filters back to fast-mode operation.

7.3.3.8 Timeout Function

The TMP75B resets the serial interface if SCL or SDA are held low for 54 ms (typ) between a start and stop

condition. If the TMP75B is pulled low, it releases the bus and then waits for a start condition. To avoid activating

the timeout function, it is necessary to maintain a communication speed of at least 1 kHz for the SCL operating

frequency.

Copyright © 2014, Texas Instruments Incorporated

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