TPS330615Q1, TPS330618Q1, TPS330620Q1, TPS330625Q1, TPS330633Q1

DUAL PROCESSOR SUPERVISORY CIRCUITS WITH POWER FAIL

SGLS241B − MARCH 2004 − REVISED APRIL 2008

5

POST OFFICE BOX 655303

saving current while using the watchdog

WDI is internally driven low during the first 7/8 of the watchdog time-out period, then momentarily pulses high,

resetting the watchdog counter. For minimum watchdog input current (minimum overall power consumption), leave

WDI low for the majority of the watchdog time-out period, pulsing it low-high-low once within 7/8 of the watchdog

time-out period to reset the watchdog timer. If, instead, WDI is externally driven high for the majority of the time-out

period, a current of 5 V/40 k

Ω ≈ 125 µA can flow into WDI.

td

td

t(tout)

VDD

VIT

WDI

RESET

t

t

t

Figure 1. Watchdog Timing

power-fail comparator (PFI and PFO)

An additional comparator is provided to monitor voltages other than the nominal supply voltage. The power-fail-input

(PFI) is compared with an internal voltage reference of 1.25 V. If the input voltage falls below the power-fail threshold

the output returns to high. By connecting two external resistors, it is possible to supervise any voltages above 1.25 V.

The sum of both resistors should be approximately 1 M

Ω, to minimize power consumption and also to ensure that the

current in the PFI pin can be neglected compared with the current through the resistor network. The tolerance of the

external resistors should be not more than 1% to ensure minimal variation of sensed voltage. If the power-fail

comparator is unused, connect PFI to ground and leave PFO unconnected.

PFI

PFO

VCC

GND

TPS3306

V(SENSE)

R1

1%

R2

1%

VPFI,trip = 1.25 V ×

R1 + R2

R2