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FAN53541UCX Datasheet(PDF) 3 Page - Fairchild Semiconductor |
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FAN53541UCX Datasheet(HTML) 3 Page - Fairchild Semiconductor |
3 / 15 page © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN53541 • Rev. 1.0.2 3 Pin Configuration Figure 2. Top View Figure 3. Top View Bottom View Pin Definitions Bump # Name Description A1 PGOOD Power Good. This open-drain pin pulls LOW if the output falls out of regulation or is in soft-start. A2 EN Enable. The device is in Shutdown Mode when this pin is LOW. Do not leave this pin floating. A3 FB FB. Connect to resistor divider. The IC regulates this pin to 0.8 V. A4 VOUT VOUT. Sense pin for VOUT. Connect directly to COUT. B1 MODE MODE / SYNC. A logic 0 allows the IC to automatically switch to PFM during light loads. When held HIGH, the IC to stays in PWM Mode. The regulator also synchronizes its switching frequency to four times (4X) the frequency provided on this pin (fMODE). Do not leave this pin floating. B2, B3, C1 – C4 GND Ground. Low-side MOSFET is referenced to this pin. CIN and COUT should be returned with a minimal path to these pins. B4 AGND Analog Ground. All signals are referenced to this pin. Avoid routing high dV/dt AC currents through this pin. D1, D2, E1, E2 VIN Power Input Voltage. Connect to input power source. Connect to CIN with minimal path. D3, D4, E3, E4 SW Switching Node. Connect to inductor. PGOOD GND C1 B1 A1 A2 C3 B3 A3 C2 D1 D3 D2 B2 C4 B4 A4 D4 E1 E3 E2 E4 EN FB VOUT MODE VIN SW C1 B1 A1 C3 B3 A3 A2 C2 D1 D3 D2 B2 C4 B4 A4 D4 E1 E3 E2 E4 |
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