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SI599 Datasheet(PDF) 1 Page - Silicon Laboratories |
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SI599 Datasheet(HTML) 1 Page - Silicon Laboratories |
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1 / 28 page  Rev. 1.0 11/11 Copyright © 2011 by Silicon Laboratories Si598/Si599 Si598/Si599 10–810 M H Z I 2C P ROGRAMMABLE XO/VCXO Features Applications Description The Si598 XO/Si599 VCXO utilizes Silicon Laboratories' advanced DSPLL® circuitry to provide a low-jitter clock at any frequency. They are user- programmable to any output frequency from 10 to 810 MHz with 28 parts per trillion (PPT) resolution. The device is programmed via a 2-pin I2C compatible serial interface. The wide frequency range and ultra-fine programming resolution make these devices ideal for applications that require in-circuit dynamic frequency adjustments or multi-rate operation with non-integer related rates. Using an integrated crystal, these devices provide stable low jitter frequency synthesis and replace multiple XOs, clock generators, and DAC controlled VCXOs. Functional Block Diagram I2C programmable output frequencies from 10 to 810 MHz 0.5 ps RMS phase jitter Superior power supply rejection: 0.3–0.4 ps additive jitter Available LVPECL, CMOS, LVDS, and CML outputs 1.8, 2.5, or 3.3 V supply Pin- and register-compatible with Si570/571 Programmable with 28 parts per trillion frequency resolution Integrated crystal provides stability and low phase noise Frequency changes up to ±3500 ppm are glitchless –40 to 85 °C operation Industry-standard 5x7 mm package SONET / SDH / xDSL Ethernet / Fibre Channel 3G SDI / HD SDI Multi-rate PLLs Multi-rate reference clocks Frequency margining Digital PLLs CPU / FPGA FIFO control Adaptive synchronization Agile RF local oscillators VDD Fixed Frequency Oscillator CLK+ CLK– OE GND Power Supply Filtering I2C Interface SDA SCL ADC Vc (Si599) Any Frequency DSPLL® 10 to 810 MHz Clock Synthesis Ordering Information: See page 22. Pin Assignments: See page 21. (Top View) Si5602 Si598 Si599 1 2 3 6 5 4 NC GND OE VDD CLK+ CLK– SDA SCL 8 7 1 2 3 6 5 4 VC GND OE VDD CLK+ CLK– SDA SCL 8 7 |
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