Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
AD7402-8BRIZ-RL Datasheet(PDF) 4 Page - Analog Devices |
|
AD7402-8BRIZ-RL Datasheet(HTML) 4 Page - Analog Devices |
4 / 20 page AD7402 Data Sheet Rev. A | Page 4 of 20 TIMING SPECIFICATIONS VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, TA = −40°C to +105°C, unless otherwise noted. Table 2. Parameter1 Min Typ Max Unit Description fMCLKOUT2 9.4 10 10.6 MHz Master clock output frequency t13 ±10 ns Data access time after MCLKOUT rising edge t23 44 ns Data hold time after MCLKOUT falling edge t3 33 ns Master clock low time t4 33 ns Master clock high time 1 Sample tested during initial release to ensure compliance. 2 Mark space ratio for clock output is 45/55 to 55/45. 3 Defined as the time required for the output to cross 0.8 V or 2.0 V for VDD2 = 3 V to 3.6 V, or when the output crosses 0.8 V or 0.7 × VDD2 for VDD2 = 4.5 V to 5.5 V, as outlined in Figure 2. Measured with a ±200 μA load and a 25 pF load capacitance. Figure 2. Data Timing 1 SEE NOTE 3 OF TABLE 2 FOR FURTHER DETAILS. MDAT MCLKOUT 2.0V OR 0.7V × VDD21 2.0V OR 0.7V × VDD21 t4 t1 t2 t3 0.8V 0.8V |
Número de pieza similar - AD7402-8BRIZ-RL |
|
Descripción similar - AD7402-8BRIZ-RL |
|
|
Enlace URL |
Política de Privacidad |
ALLDATASHEET.ES |
¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |