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SI52112-B5 Datasheet(PDF) 1 Page - Silicon Laboratories |
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SI52112-B5 Datasheet(HTML) 1 Page - Silicon Laboratories |
1 / 20 page Rev 1.2 12/15 Copyright © 2015 by Silicon Laboratories Si52112-B5/B6 Si52112-B5/B6 PCI-E XPRESS G EN 3 DUAL O UTPUT C LOCK G ENERATOR Features Applications Description Si52112-B5/B6 is a high-performance, PCIe clock generator that can source two PCIe clocks from a 25 MHz crystal or clock input. The clock outputs are compliant to PCIe Gen 1, Gen 2, Gen 3, Gen 3 SRNS and Gen 4 common clock specifications. The ultra-small footprint (3x3 mm) and industry leading low power consumption make Si52112-B5/B6 the ideal clock solution for consumer and embedded applications. Measuring PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at www.silabs.com/pcie-learningcenter. Functional Block Diagram PCI-Express Gen 1, Gen 2, Gen 3, and Gen 4 common clock compliant Gen 3 SRNS Compliant Low power HCSL differential output buffers Supports Serial-ATA (SATA) at 100 MHz No termination resistors required 25 MHz Crystal Input or Clock input Triangular spread spectrum profile for maximum EMI reduction (Si52112-B6) Extended Temperature: –40 to 85 °C 3.3 V Power supply Small package 10-pin TDFN (3x3 mm) Si52112-B5 does not support spread spectrum outputs Si52112-B6 supports 0.5% down spread outputs Network attached storage Multi-function printer Wireless access point Routers XIN/CLKIN XOUT DIFF2 DIFF1 PLL Divider VDD VSS Patents pending Ordering Information: See page 13 Pin Assignments 10 9 8 7 1 2 3 4 VDD VDD XOUT XIN/CLKIN VSS VSS 5 6 DIFF1 DIFF1 DIFF2 DIFF2 |
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