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SI52143 Datasheet(PDF) 6 Page - Silicon Laboratories |
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SI52143 Datasheet(HTML) 6 Page - Silicon Laboratories |
6 / 21 page Si52143 6 Rev 1.3 Spread Range SPR-2 Down spread — –0.5 — % Modulation Frequency FMOD 30 31.5 33 kHz REF(25 MHz) at 3.3 V Duty Cycle TDC Measurement at 1.5 V 45 — 55 % Rising and Falling Edge Rate TR / TF Measured between 0.8 and 2.0 V 1.0 — 4.0 V/ns Cycle to Cycle Jitter TCCJ Measurement at 1.5 V — — 300 ps Long Term Accuracy LACC Measured at 1.5 V — — 100 ppm Enable/Disable and Set-Up Clock Stabilization from Power-up TSTABLE —— 1.8 ms Stopclock Set-up Time TSS 10.0 — — ns Table 3. Absolute Maximum Conditions Parameter Symbol Test Condition Min Typ Max Unit Main Supply Voltage VDD_3.3V Functional — — 4.6 V Input Voltage VIN Relative to VSS –0.5 — 4.6 VDC Temperature, Storage TS Non-functional –65 — 150 °C Temperature, Operating Ambient TA Functional –40 — 85 °C Temperature, Junction TJ Functional — — 150 °C Dissipation, Junction to Case ØJC JEDEC (JESD 51) — — 35 °C/W Dissipation, Junction to Ambient ØJA JEDEC (JESD 51) — — 37 °C/W ESD Protection (Human Body Model) ESDHBM JEDEC (JESD 22-A114) 2000 — — V Flammability Rating UL-94 UL (Class) V–0 Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required. Table 2. AC Electrical Specification (Continued) Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. Visit www.pcisig.com for complete PCIe specifications. 2. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5. 3. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter. |
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