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SI53115 Datasheet(PDF) 9 Page - Silicon Laboratories

No. de pieza SI53115
Descripción Electrónicos  15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER
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Fabricante Electrónico  SILABS [Silicon Laboratories]
Página de inicio  http://www.silabs.com
Logo SILABS - Silicon Laboratories

SI53115 Datasheet(HTML) 9 Page - Silicon Laboratories

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Si53115
Rev. 1.1
9
Additive Phase Jitter
Bypass Mode
PCIe Gen 11,2,3
—10—
ps
PCIe Gen 2 Low Band
F < 1.5 MHz1,3,4,5
—1.0
ps
(RMS)
PCIe Gen 2 High Band
1.5 MHz < F < Nyquist1,3,4,5
—1.0
ps
(RMS)
PCIe Gen 3
(PLL BW 2–4 MHz, CDR = 10 MHz)1,3,4,5
—0.3
ps
(RMS)
PCIe Gen 4, Common Clock
(PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz)1,4,5,8
—0.3
ps
(RMS)
Intel QPI & Intel® SMI
(4.8 Gbps or 6.4 Gb/s, 100 or 133 MHz, 12 UI)1,6,7
—0.12—
ps
(RMS)
Intel QPI & Intel® SMI
(8 Gb/s, 100 MHz, 12 UI)1,6
—0.1
ps
(RMS)
Intel QPI & Intel® SMI
(9.6 Gb/s, 100 MHz, 12 UI)1,6
—0.1
ps
(RMS)
Table 6. Phase Jitter (Continued)
Notes:
1.
Post processed evaluation through Intel supplied Matlab* scripts. Defined for a BER of 1E-12. Measured values at a
smaller sample size have to be extrapolated to this BER target.
2.
ζ = 0.54 implies a jitter peaking of 3 dB.
3.
PCIe* Gen3 filter characteristics are subject to final ratification by PCISIG. Check the PCI-SIG for the latest
specification.
4.
Measured on 100 MHz PCIe output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.
5.
Measured on 100 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.
6.
Measured on 100 MHz, 133 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.
7.
These jitter numbers are defined for a BER of 1E-12. Measured numbers at a smaller sample size have to be
extrapolated to this BER target.
8.
Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
9.
Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.


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