Si53154

Rev. 1.1

7

2. Functional Description

2.1. OE Pin Definition

The OE pins are active high inputs used to enable and disable the output clocks. To enable the output clock, the OE

to be driven at all times even though they have an internal 100 k

 resistor.

2.2. OE Assertion

The OE signals are active high inputs used for synchronous stopping and starting the DIFF output clocks respectively

while the rest of the clock generator continues to function. The assertion of the OE signal by making it logic high

causes stopped respective DIFF outputs to resume normal operation. No short or stretched clock pulses are

produced when the clock resumes. The maximum latency from the assertion to active outputs is no more than two

to six output clock cycles.

2.3. OE Deassertion

When the OE pin is deasserted by making it logic low, the corresponding DIFF output is stopped, and the final output

state is driven low.