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SI53306 Datasheet(PDF) 1 Page - Silicon Laboratories |
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SI53306 Datasheet(HTML) 1 Page - Silicon Laboratories |
1 / 29 page Rev. 1.0 2/15 Copyright © 2015 by Silicon Laboratories Si53306 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA). Si53306 1:4 L OW-J ITTER U NIVERSAL B UFFER/L EVEL TRANSLATOR Features Applications Description The Si53306 is an ultra low jitter four output differential buffer with pin-selectable output clock signal format. The Si53306 utilizes Silicon Laboratories' advanced CMOS technology to fanout clocks from 1 to 725 MHz with guaranteed low additive jitter, low skew, and low propagation delay variability. The Si53306 features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. Independent core and output bank supply pins provide integrated level translation without the need for external circuitry. Functional Block Diagram 4 differential or 8 LVCMOS outputs Ultra-low additive jitter: 45 fs rms Wide frequency range: 1 to 725 MHz Any-format input with pin selectable output formats: LVPECL, low power LVPECL, LVDS, CML, HCSL, LVCMOS Synchronous output enable Independent VDD and VDDO : 1.8/2.5/3.3 V 1.2/1.5 V LVCMOS output support Selectable LVCMOS drive strength to tailor jitter and EMI performance Small size: 16-QFN (3 mm x 3 mm) RoHS compliant, Pb-free Industrial temperature range: –40 to +85 °C High-speed clock distribution Ethernet switch/router Optical Transport Network (OTN) SONET/SDH PCI Express Gen 1/2/3 Storage Telecom Industrial Servers Backplane clock distribution VDD Power Supply Filtering VDDO OE SFOUT[1:0] CLK CLK Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Patents pending Ordering Information: See page 24. Pin Assignments GND PAD 9 11 10 12 4 2 3 1 CLK CLK Q1 Q1 Q2 Q2 GND VDD |
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