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SI53321 Datasheet(PDF) 1 Page - Silicon Laboratories |
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SI53321 Datasheet(HTML) 1 Page - Silicon Laboratories |
1 / 28 page Rev. 1.0 4/15 Copyright © 2015 by Silicon Laboratories Si53321 Si53321 1:10 L OW J ITTER LVPECL C LOCK B UFFER WITH 2:1 I NPUT M UX (< 1.25 GH Z) Features Applications Description The Si53321 is an ultra-low jitter ten output differential buffer. The Si53321 features a 2:1 input mux, making it ideal for redundant clocking applications. The Si53321 utilizes Silicon Laboratories' advanced CMOS technology to fanout clocks from dc to 1.25 GHz with guaranteed low additive jitter, low skew, and low propagation delay variability. The Si53321 features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. Functional Block Diagram 10 LVPECL outputs Ultra-low additive jitter: 45 fs rms typ Wide frequency range: dc to 1.25 GHz Input compatible with LVPECL, LVDS, CML, HCSL, LVCMOS 2:1 input mux Low output-output skew: 25 ps (typ) RoHS compliant, Pb-free 32-QFN, 32-eLQFP Industrial temperature range: –40 to +85°C Footprint-compatible with MC100LVEP111, CDCLVP111, MAX9311, ICS853S111BI, ICS85310-1 High-speed clock distribution Ethernet switch/router Optical Transport Network (OTN) SONET/SDH PCI Express Gen 1/2/3 Storage Telecom Industrial Servers Backplane clock distribution CLK0 CLK0 CLK1 CLK1 0 1 CLK_SEL Power Supply Filtering Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 Q7 Q8 Q8 Q9 Q9 VDD GND Patents pending Ordering Information: See page 19. Pin Assignments (Top View) 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 Q3 24 Q3 23 22 Q4 21 20 Q5 19 18 Q6 17 Q4 Q5 Q6 VDD 1 CLK_SEL 2 3 CLK0 4 5 CLK1 6 7 GND 8 CLK0 NC CLK1 Exposed GND Pad VDD 1 CLK_SEL 2 3 CLK0 4 5 CLK1 6 7 GND 8 CLK0 NC CLK1 Q3 24 Q3 23 22 Q4 21 20 Q5 19 18 Q6 17 Q4 Q5 Q6 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 Exposed GND Pad |
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