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CDCEL824PWR Datasheet(PDF) 11 Page - Texas Instruments |
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CDCEL824PWR Datasheet(HTML) 11 Page - Texas Instruments |
11 / 33 page CDCEL824 Slave Master SDA SCL R P R P C BUS C BUS P S P SCL SDA VIH VIL VIH VIL A Bit7(MSB) Bit6 Bit0(LSB) tw(SCLL) tw(SCLH) tr tf tsu(START) th(START) tsu(SDA) th(SDA) t(BUS) tr tf tsu(STOP) CDCEL824 www.ti.com SCAS945A – JUNE 2015 – REVISED SEPTEMBER 2015 9.3.2 SDA/SCL Serial Interface This section describes the SDA/SCL interface of the CDCEL824 device. The CDCEL824 operates as a slave device of the 2-wire serial SDA/SCL bus, compatible with the popular SMBus or I2C specification. It operates in the standard-mode transfer (up to 100 kbit/s) and fast-mode transfer (up to 400 kbit/s) and supports 7-bit addressing. The SDA/S1 and SCL/S2 pins of the CDCEL824 are dual-function pins. In the default configuration they are used as SDA/SCL serial programming interface. They can be reprogrammed as general-purpose control pins, S1 and S2, by changing the corresponding EEPROM setting, byte 02h, bit [6]. Figure 5. Timing Diagram for SDA/SCL Serial Control Interface 9.3.3 SDA/SCL Hardware Interface Figure 6 shows how the CDCEL824 clock synthesizer is connected to the SDA/SCL serial interface bus. Multiple devices can be connected to the bus, but the speed may need to be reduced (400 kHz is the maximum) if many devices are connected. Note that the pullup resistors (RP) depend on the supply voltage, bus capacitance, and number of connected devices. The recommended pullup value is 4.7 k Ω. It must meet the minimum sink current of 3 mA at VOLmax = 0.4 V for the output stages (for more details see the SMBus or I2C Bus specification). Figure 6. SDA/SCL Hardware Interface Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: CDCEL824 |
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