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SI53365 Datasheet(PDF) 4 Page - Silicon Laboratories |
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SI53365 Datasheet(HTML) 4 Page - Silicon Laboratories |
4 / 14 page Si53365 4 Rev. 1.0 Table 5. AC Characteristics (VDD =1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Frequency F LVCMOS dc — 200 MHz Duty Cycle Note: 50% input duty cycle. DC 200 MHz, 50 Ω to VDD/2, 20/80% TR/TF<10% of period 40 50 60 % Minimum Input Clock Slew Rate SR Required to meet prop delay and additive jitter specifications (20–80%) 0.75 — — V/ns Output Rise/Fall Time TR/TF 200 MHz, 50 Ω, 20/80%, 2 pF load, 12 mA drive strength —— 850 ps Minimum Input Pulse Width TW 2— — ns Additive Jitter (12 kHz – 20 MHz) J3.3 V, 200 MHz, Vin=1.7VPP @ 1 V/ns — 130 180 fs-rms 3.3 V, 156.25 MHz, Vin = 2.18 VPP @ 1 V/ns — 125 220 fs-rms 2.5V, 200 MHz, Vin=1.7VPP @ 1 V/ns — 115 250 fs-rms 2.5 V, 156.25 MHz, Vin = 2.18 VPP @ 1 V/ns — 125 240 fs-rms Propagation Delay TPLH, TPHL Low-to-high, high-to-low Single-ended, CL =2pF 1.5 3.0 4.5 ns Output Enable Time TEN F=1MHz — 10 — ns F = 100 MHz — 10 — ns Output Disable Time TDIS F=1MHz — 20 — ns F = 100 MHz — 20 — ns Part to Part Skew TSKPP CL =2pF 0 — 300 ps Output to Output Skew TSK CL = 2 pF — 40 125 ps |
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