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SL23EP09SI-1HT Datasheet(PDF) 1 Page - Silicon Laboratories

No. de pieza SL23EP09SI-1HT
Descripción Electrónicos  Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer
Download  14 Pages
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Fabricante Electrónico  SILABS [Silicon Laboratories]
Página de inicio  http://www.silabs.com
Logo SILABS - Silicon Laboratories

SL23EP09SI-1HT Datasheet(HTML) 1 Page - Silicon Laboratories

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Rev 2.0, May 12, 2008
Page 1 of 14
2400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
SL23EP09
Key Features
• 10 to 220 MHz operating frequency range
• Low output clock skew: 45ps-typ
• Low output clock jitter:
 50 ps-typ cycle-to-cycle jitter
 20 ps-typ period jitter
• Low part-to-part output skew: 90 ps-typ
• Wide 2.5 V to 3.3 V power supply range
• Low power dissipation:
 26 mA-max at 66 MHz and VDD=3.3 V
 24 mA-max at 66 MHz and VDD=2.5V
• One input drives 9 outputs organized as 4+4+1
• Select mode to bypass PLL or tri-state outputs
• SpreadThru™ PLL that allows use of SSCG
• Standard and High-Drive options
• Available in 16-pin SOIC and TSSOP packages
• Available in Commercial and Industrial grades
Applications
• Printers, MFPs and Digital Copiers
• PCs and Work Stations
• Routers, Switchers and Servers
• Digital Embeded Systems
Description
The SL23EP09 is a low skew, low jitter and low power Zero
Delay Buffer (ZDB) designed to produce up to nine (9) clock
outputs from one (1) reference input clock, for high speed
clock distribution applications.
The product has an on-chip PLL which locks to the input
clock at CLKIN and receives its feedback internally from the
CLKOUT pin.
The SL23EP09 has two (2) clock driver banks each with four
(4) clock outputs. These outputs are controlled by two (2)
select input pins S1 and S2. When only four (4) outputs are
needed, four (4) bank-B output clock buffers can be tri-stated
to reduce power dissipation and jitter. The select inputs can
also be used to tri-state both banks A and B or drive them
directly from the input bypassing the PLL and making the
product behave like a Non-Zero Delay Buffer (NZDB).
The high-drive version operates up to 220MHz and 200MHz
at 3.3V and 2.5V power supplies respectively.
Benefits
• Up to nine (9) distribution of input clock
• Standard and High-Dirive levels to control impedance
level, frequency range and EMI
• Low power dissipation, jitter and skew
• Low cost
Block Diagram
Low Power and
Low Jitter
PLL
MUX
Input Selection
Decoding Logic
VDD
GND
2
2
S2
S1
CLKIN
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)


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