TS1001IJ5T datasheet(3/12 Pages) SILABS

No. de pieza	TS1001IJ5T

Descripción Electrónicos	THE ONLY 0.8V/0.6A RAIL-TO-RAIL OP AMP

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Fabricante Electrónico	SILABS [Silicon Laboratories]

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TS1001

TS1001 Rev. 1.0

Page 3

ELECTRICAL CHARACTERISTICS

VDD = +0.8V, VSS = 0V, VINCM = VSS; RL = 100kΩ to (VDD-VSS)/2; TA = -40°C to +85°C, unless otherwise noted.

Typical values are at TA = +25°C. See Note 1

Parameters

Symbol

Conditions

Min

Typ

Max

Units

Supply Voltage Range

VDD-VSS

0.65

0.8

2.5

V

Supply Current

ISY

RL = Open circuit

TA = 25°C

0.6

0.8

µA

-40°C ≤ TA ≤ 85°C

1

Input Offset Voltage

VOS

VIN = VSS or VDD

TA = 25°C

0.5

3

mV

-40°C ≤ TA ≤ 85°C

6

Input Offset Voltage Drift

TCVOS

20

µV/°C

Input Bias Current

IIN+, IIN-

VIN+, VIN- = (VDD - VSS)/2

TA = 25°C

0.025

nA

-40°C ≤ TA ≤ 85°C

20

Input Offset Current

IOS

Specified as IIN+ - IIN-

VIN+, VIN- = (VDD - VSS)/2

TA = 25°C

0.01

nA

-40°C ≤ TA ≤ 85°C

2

Input Voltage Range

IVR

Guaranteed by Input Offset Voltage Test

VSS

VDD

V

Common-Mode Rejection Ratio

CMRR

0V ≤ VIN(CM) ≤ 0.4V

50

74

dB

Power Supply Rejection Ratio

PSRR

0.65V ≤ (VDD - VSS) ≤ 2.5V

50

74

dB

Output Voltage High

VOH

Specified as VDD - VOUT,

RL = 100kΩ to VSS

TA = 25°C

1.2

2

mV

-40°C ≤ TA ≤ 85°C

2.5

Specified as VDD - VOUT,

RL = 10kΩ to VSS

TA = 25°C

10

16

-40°C ≤ TA ≤ 85°C

20

Output Voltage Low

VOL

Specified as VOUT - VSS,

RL = 100kΩ to VDD

TA = 25°C

0.4

0.6

mV

-40°C ≤ TA ≤ 85°C

1

Specified as VOUT - VSS,

RL = 10kΩ to VDD

TA = 25°C

5

7

-40°C ≤ TA ≤ 85°C

10

Short-circuit Current

ISC+

VOUT = VSS

TA = 25°C

0.5

1.5

mA

-40°C ≤ TA ≤ 85°C

0.3

ISC-

VOUT = VDD

TA = 25°C

4.5

11

-40°C ≤ TA ≤ 85°C

3

Open-loop Voltage Gain

AVOL

VSS+50mV ≤ VOUT ≤ VDD-50mV

TA = 25°C

90

104

dB

-40°C ≤ TA ≤ 85°C

85

Gain-Bandwidth Product

GBWP

RL = 100kΩ to VSS, CL = 20pF

4

kHz

Phase Margin

φM

Unity-gain Crossover,

RL = 100kΩ to VSS, CL = 20pF

70

degrees

Slew Rate

SR

RL = 100kΩ to VSS, AVCL = +1V/V

1.5

V/ms

Full-power Bandwidth

FPBW

FPBW = SR/(π • VOUT,PP); VOUT,PP = 0.7VPP

680

Hz

Input Voltage Noise Density

en

f = 1kHz

0.6

µV/

√Hz

Input Current Noise Density

in

f = 1kHz

10

pA/

√Hz

Note 1: All specifications are 100% tested at TA = +25°C. Specification limits over temperature (TA = TMIN to TMAX) are guaranteed by

device characterization, not production tested.

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