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TPD4E02B04DQAR Datasheet(PDF) 9 Page - Texas Instruments |
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TPD4E02B04DQAR Datasheet(HTML) 9 Page - Texas Instruments |
9 / 21 page IO4 GND IO3 IO2 IO1 9 TPD4E02B04 www.ti.com SLVSD85A – NOVEMBER 2015 – REVISED FEBRUARY 2016 Product Folder Links: TPD4E02B04 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated 7 Detailed Description 7.1 Overview The TPD4E02B04 is a bidirectional ESD Protection Diode with ultra-low capacitance. This device can dissipate ESD strikes above the maximum level specified by the IEC 61000-4-2 International Standard. The ultra-low capacitance makes this device ideal for protecting any super high-speed signal pins. 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 IEC 61000-4-2 ESD Protection The I/O pins can withstand ESD events up to ±12-kV contact and ±15-kV air gap. An ESD/surge clamp diverts the current to ground. 7.3.2 IEC 61000-4-4 EFT Protection The I/O pins can withstand an electrical fast transient burst of up to 80 A (5/50 ns waveform, 4 kV with 50 Ω impedance). An ESD/surge clamp diverts the current to ground. 7.3.3 IEC 61000-4-5 Surge Protection The I/O pins can withstand surge events up to 2 A and 17 W (8/20 µs waveform). An ESD/surge clamp diverts this current to ground. 7.3.4 IO Capacitance The capacitance between each I/O pin to ground is 0.27 pF (typical) and 0.37 pF (maximum). This device supports data rates up to 10 Gbps. 7.3.5 DC Breakdown Voltage The DC breakdown voltage of each I/O pin is a minimum of ±5.5 V. This ensures that sensitive equipment is protected from surges above the reverse standoff voltage of ±3.6 V. 7.3.6 Ultra Low Leakage Current The I/O pins feature an ultra-low leakage current of 10 nA (max) with a bias of ±2.5 V 7.3.7 Low ESD Clamping Voltage The I/O pins feature an ESD clamp that is capable of clamping the voltage to 8.8 V (IPP = 5 A). 7.3.8 Supports High Speed Interfaces This device is capable of supporting high speed interfaces up to 10 Gbps, because of the extremely low IO capacitance. |
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