TPD7S019

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SLLSE33C – AUGUST 2010 – REVISED NOVEMBER 2015

10 Layout

10.1 Layout Guidelines

The optimum placement of this device is as close to the connector as possible. EMI during an ESD event can

couple from the trace being struck to other nearby unprotected traces, resulting in early system failures.

Therefore, the PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected

traces away from the protected traces which are between the TVS and the connector.

Route the protected traces as straight as possible.

Avoid using VIAs between the connecter and an I/O protection pin on TPD7S019.

Avoid 90º turns in traces since electric fields tend to build up on corners, increasing EMI coupling.

Minimize impedance on the path to GND for maximum ESD dissipation.

The VIDEO lines internal protection circuits are the same and thus these pins are interchangeable for routing.

10.2 Layout Example

Figure 9. Simplified Layout With TPD7S019 (Only IO Lines are Shown)

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Product Folder Links: TPD7S019