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STHVDAC-256MTG Datasheet(PDF) 7 Page - STMicroelectronics |
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STHVDAC-256MTG Datasheet(HTML) 7 Page - STMicroelectronics |
7 / 27 page DocID028369 Rev 1 7/27 STHVDAC-256MTG Theory of operation 27 3 Theory of operation 3.1 HVDAC output voltages The HVDAC outputs are directly controlled by programming the 7 bits DAC (DAC A to DAC F) through the RFFE interface. The DAC stages are driven from a reference voltage, generating an analog output voltage driving a high voltage amplifier supplied from the boost converter (see HVDAC block diagram Figure 2). The HVDAC output voltages are scaled from 0 to 24 V, with 127 steps of 188 mV. If DAC value is set to 00h, then the corresponding output is setup to be in high impedance state (6 MΩ). STHVDAC-256MTG has been specifically designed to drive BST tunable capacitors, equivalent to RC output loads as shown in Figure 3. Figure 3. HVDAC output load Each DAC output can be operated either in normal, turbo or glide mode. The DAC mode is set by controlling turbo mode bit of each DAC register (MSB of registers 2, 3, 4, 6, 7, 8), and Glide_enable bits (defined in registers#1 and #5). 3.1.1 DAC operation in normal mode -- glide_enable = 0b, turbo_mode = 0b In normal mode, the DAC output directly switches from old to new output voltage after programming. The DAC output is controlled to ensure the output voltage (Vout, see Figure 3) reaches its final value within 10µs typical after valid RFFE command. Typical timing diagram in Normal mode is shown on Figure 4. |
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