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74F193PC Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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74F193PC Datasheet(HTML) 2 Page - National Semiconductor (TI) |
2 / 10 page Unit LoadingFan Out 54F74F Pin Names Description UL Input IIH IIL HIGHLOW Output IOH IOL CPU Count Up Clock Input (Active Rising Edge) 1030 20 mA b18 mA CPD Count Down Clock Input (Active Rising Edge) 1030 20 mA b18 mA MR Asynchronous Master Reset Input (Active HIGH) 1010 20 mA b06 mA PL Asynchronous Parallel Load Input (Active LOW) 1010 20 mA b06 mA P0–P3 Parallel Data Inputs 1010 20 mA b06 mA Q0–Q3 Flip-Flop Outputs 50333 b 1 mA20 mA TCD Terminal Count Down (Borrow) Output (Active LOW) 50333 b 1 mA20 mA TCU Terminal Count Up (Carry) Output (Active LOW) 50333 b 1 mA20 mA Functional Description The ’F193 is a 4-bit binary synchronous updown (revers- ible) counter It contains four edge-triggered flip-flops with internal gating and steering logic to provide master reset individual preset count up and count down operations A LOW-to-HIGH transition on the CP input to each flip-flop causes the output to change state Synchronous switching as opposed to ripple counting is achieved by driving the steering gates of all stages from a common Count Up line and a common Count Down line thereby causing all state changes to be initiated simultaneously A LOW-to-HIGH transition on the Count Up input will advance the count by one a similar transition on the Count Down input will de- crease the count by one While counting with one clock in- put the other should be held HIGH as indicated in the Function Table The Terminal Count Up (TCU) and Terminal Count Down (TCD) outputs are normally HIGH When the circuit has reached the maximum count state 15 the next HIGH-to- LOW transition of the Count Up Clock will cause TCU to go LOW TCU will stay LOW until CPU goes HIGH again thus effectively repeating the Count Up Clock but delayed by two gate delays Similarly the TCD output will go LOW when the circuit is in the zero state and the Count Down Clock goes LOW Since the TC outputs repeat the clock wave- forms they can be used as the clock input signals to the next higher order circuit in a multistage counter TCU e Q0 Q1 Q2 Q3 CPU TCD e Q0 Q1 Q2 Q3 CPD The ’F193 has an asynchronous parallel load capability per- mitting the counter to be preset When the Parallel Load (PL) and the Master Reset (MR) inputs are LOW informa- tion present on the Parallel Data input (P0–P3) is loaded into the counter and appears on the outputs regardless of the conditions of the clock inputs A HIGH signal on the Master Reset input will disable the preset gates override both clock inputs and latch each Q output in the LOW state If one of the clock inputs is LOW during and after a reset or load operation the next LOW-to-HIGH transition of that clock will be interpreted as a legitimate signal and will be counted Function Table MR PL CPU CPD Mode H X X X Reset (Asyn) L L X X Preset (Asyn) L H H H No Change LH L H Count Up LH H L Count Down H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial L e LOW-to-HIGH Clock Transition State Diagram TLF9497 – 5 2 |
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