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LSF0204 Datasheet(PDF) 1 Page - Texas Instruments |
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LSF0204 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 32 page Vref_A Vref_B EN GND A1 A2 A3 A4 B1 B2 B3 B4 LSF0204 SW SW SW SW Product Folder Sample & Buy Technical Documents Tools & Software Support & Community LSF0204, LSF0204D SLVSCP5D – JULY 2014 – REVISED DECEMBER 2015 LSF0204x 4-Bits Bidirectional Multi-Voltage Level Translator for Open-Drain and Push- Pull Application 1 Features 3 Description The LSF family consists of bidirectional voltage level 1 • Provides Bidirectional Voltage Translation With No translators that operate from 0.8 V to 4.5 V (Vref_A) Direction Terminal and 1.8 V to 5.5 V (Vref_B). This range allows for • Supports up to 100-MHz up Translation and bidirectional voltage translations between 0.8 V and Greater Than 100-MHz Down Translation 5.0 V without the need for a direction terminal in at ≤ 30-pF Capacitor Load and up to 40-MHz open-drain or push-pull applications. The LSF family Up/Down Translation at 50-pF Capacitor Load supports level translation applications with transmission speeds greater than 100 MHz for open- • Supports Ioff, Partial Power Down Mode (Refer to drain systems that utilize a 15-pF capacitance and Feature Description) 165- Ω pull-up resistor. • Allows Bidirectional Voltage Level Translation When the An or Bn port is LOW, the switch is in the Between ON-state and a low resistance connection exists – 0.8 V ↔ 1.8, 2.5, 3.3, 5 V between the An and Bn ports. The low Ron of the – 1.2 V ↔ 1.8, 2.5, 3.3, 5 V switch allows connections to be made with minimal propagation delay and signal distortion. The voltage – 1.8 V ↔ 2.5, 3.3, 5 V on the A or B side will be limited to Vref_A and can – 2.5 V ↔ 3.3, 5 V be pulled up to any level between Vref_A and 5 V. – 3.3 V ↔ 5 V This functionality allows a seamless translation • Low Standby Current between higher and lower voltages selected by the user without the need for directional control. • 5 V Tolerance I/O Port to Support TTL • Low Ron Provides Less Signal Distortion Device Information(1) • High-Impedance I/O Terminals For EN = Low PART NUMBER PACKAGE BODY SIZE (NOM) • Flow-Through Pinout for Ease PCB Trace Routing TSSOP (14) 5.00 mm × 4.40 mm • Latch-Up Performance Exceeds 100 mA Per UQFN (12) 2.00 mm × 1.70 mm LSF0204x JESD17 VQFN (14) 3.50 mm × 3.50 mm • –40°C to 125°C Operating Temperature Range DSBGA (12) 1.90 mm × 1.40 mm • ESD Performance Tested Per JESD 22 (1) For all available packages, see the orderable addendum at the end of the datasheet. – 2000-V Human-Body Model (A114-B, Class II) – 200-V Machine Model (A115-A) Simplified Schematic – 1000-V Charged-Device Model (C101) 2 Applications • GPIO, MDIO, PMBus, SMBus, SDIO, UART, I2C, and Other Interfaces in Telecom Infrastructure • Industrial • Automotive • Personal Computing 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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