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LSF0204DYZPR Datasheet(PDF) 11 Page - Texas Instruments |
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LSF0204DYZPR Datasheet(HTML) 11 Page - Texas Instruments |
11 / 32 page LSF0204, LSF0204D www.ti.com SLVSCP5D – JULY 2014 – REVISED DECEMBER 2015 10.3 Feature Description 10.3.1 Support High Speed Translation, Greater than 100 MHz Allows the LSF family to support more consumer or telecom interfaces (MDIO or SDIO). 10.3.2 Bidirectional Voltage Translation Without DIR Terminal Minimizes system effort to develop voltage translation for bidirectional interface (PMBus, I2C, or SMbus). 10.3.3 5-V Tolerance on IO Port and 125°C Support The LSF family, with 5-V tolerance and 125°C support, is flexible and compliant with TTL levels in industrial and telecom applications. 10.3.4 Channel Specific Translation The LSF family is able to set up different voltage translation levels on each channel. 10.3.5 Ioff, Partial Power Down Mode When Vref_A, Vref_B = 0, all of data pins and EN pin are Hi-Z. EN logic circuit is supplied by Vref_A, once Vref_A power up first and all of data pins are unknown state until Vref_B and EN ready. No power sequence is required to enable LSF0204 and operate function normally. 10.4 Device Functional Modes Table 1 lists the device functional modes of the LSF0204x family of devices. Table 1. Function Table INPUT EN(1) TERMINAL FUNCTION H An = Bn L Hi-Z (1) EN is controlled by Vref_A logic levels. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: LSF0204 LSF0204D |
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