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SN74LV132APWRG4 Datasheet(PDF) 11 Page - Texas Instruments

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No. de pieza SN74LV132APWRG4
Descripción Electrónicos  Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs
Download  24 Pages
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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SN74LV132APWRG4 Datasheet(HTML) 11 Page - Texas Instruments

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VCC
Unused Input
Input
Output
Unused Input
Input
Output
SN54LV132A, SN74LV132A
www.ti.com
SCLS394J – APRIL 1999 – REVISED FEBRUARY 2015
Typical Application (continued)
10.2.3 Application Curve
Figure 6. Switching Characteristics Comparison
11 Power Supply Recommendations
The power supply can be any voltage between the min and max supply voltage rating located in Recommended
Operating Conditions.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, TI recommends 0.1
μF and if there are multiple VCC terminals then TI recommends .01 μF or .022 μF for
each power terminal. It is okay to parallel multiple bypass caps to reject different frequencies of noise. A 0.1
μF
and 1
μF are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal
as possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions
of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only
3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages
at the outside connections result in undefined operational states. Specified below are the rules that must be
observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low
bias to prevent them from floating. The logic level that should be applied to any particular unused input depends
on the function of the device. Generally they will be tied to GND or VCC whichever make more sense or is more
convenient. It is generally okay to float outputs unless the part is a transceiver. If the transceiver has an output
enable pin it will disable the outputs section of the part when asserted. This will not disable the input section of
the IOs so they also cannot float when disabled.
12.2 Layout Example
Figure 7. Layout Recommendation
Copyright © 1999–2015, Texas Instruments Incorporated
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Product Folder Links: SN54LV132A SN74LV132A


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