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74AVCH2T45DCTRE4 Datasheet(PDF) 4 Page - Texas Instruments |
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74AVCH2T45DCTRE4 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 31 page 4 3 2 1 5 6 7 8 GND A2 A1 VCCA DIR B2 B1 VCCB D1 D2 C2 C1 B1 B2 A1 A2 1 2 3 4 8 7 6 5 VCCA A1 A2 GND VCCB B1 B2 DIR SN74AVCH2T45 SCES582H – JULY 2004 – REVISED APRIL 2015 www.ti.com 5 Description (Continued) This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, then both outputs are in the high-impedance state. The bus-hold circuitry on the powered-up side always stays active. Active bus-hold circuitry holds unused or un-driven inputs at a valid logic state. NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. 6 Pin Configurations and Functions DCT and DCU Packages 8-Pin SSOP and VSSOP Top View YZP Package 8-Pin DSBGA Bottom View Pin Functions PIN DESCRIPTION SSOP, NAME DSBGA VSSOP VCCA 1 A1 Supply Voltage A VCCB 8 A2 Supply Voltage B GND 4 D1 Ground A1 2 B1 Output or input depending on state of DIR. Output level depends on VCCA. A2 3 C1 Output or input depending on state of DIR. Output level depends on VCCA. B1 7 B2 Output or input depending on state of DIR. Output level depends on VCCB. B2 6 C2 Output or input depending on state of DIR. Output level depends on VCCB. DIR 5 D2 Direction Pin, Connect to GND or to VCCA. 4 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN74AVCH2T45 |
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