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FWIXP425AD Datasheet(PDF) 2 Page - Intel Corporation |
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FWIXP425AD Datasheet(HTML) 2 Page - Intel Corporation |
2 / 4 page Distributed Processing Architecture (continued) The three NPEs are designed to offload many computa- tionally intensive data plane operations from the Intel XScale core. These tasks include: IP header inspection and modification; packet filtering; packet error checking; check sum computation; flag insertion and removal; PDU segmentation and assembly; and encryption. The NPE architecture includes an ALU, self-contained internal data memory, an extensive list of I/O interfaces, together with hardware acceleration engines (also known as NPE coprocessors). It is the NPE coprocessor associated with an NPE that targets a set of networking applications. Each NPE coprocessor is designed to accelerate a specific networking task that would otherwise take many MIPs to complete by a stand-alone RISC processor. Each NPE can take care of Layer 2 and, in some cases, Layer 3 packets that are passed through them. For example, the WAN/Voice NPE has one UTOPIA 2 interface and two high-speed serial interfaces so its internal processing is targeting the handling of AAL (1/2/5) SARing, TDM framing, and HDLC processing. An MII/RMII interface is attached to both the Ethernet NPE A and the Ethernet NPE B respectively. The Ethernet NPE A also has two internal coprocessors to accelerate VPN related tasks such as 3DES and Hashing at speeds up to full-rate ADSL. The Ethernet NPE B is capable of handling 100Mb/s, full-duplex Ethernet packet filtering. The extensive hardware capabilities of these NPEs are all under the management of a set of NPE microcode drivers that are released as a software library together with the Intel IXP425 network processors. Customer applications configure and interact with the NPEs through a high-performance API layer running on the Intel XScale core. Wire-Speed Performance The Intel IXP425 network processors implement a fast path design in the NPE software library to provide optimized performance for broadband applications. The fast path design passes non-inspection IP packets directly from the ingress port NPE (usually WAN/Voice NPE with the xDSL WAN port) to the egress port NPE (usually Ethernet NPE A or B with the Ethernet LAN port) without the involvement of the Intel XScale core. Since the vast majority of IP packets move from the WAN to the Ethernet LAN, isolating these data flows to the NPEs within the Intel IXP425 network processor produces a significant throughput improvement by eliminating the need to route packets through a central processor. The most demanding situation occurs when small (64 byte) IP packets are sent at the speed that saturates the physical layer (wire speed). For example, nearly 10,000 (64 byte) packets per second will be sent downstream in an ADSL connection that runs at the maximum wire speed (8 Mb/s downstream). The NPEs and fast path design in the Intel IXP425 network processors are capable of providing, at minimum packet sizes, wire-speed perfor- mance up to 52 Mb/s on the WAN side and 100 Mb/s on the Ethernet LAN. |
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