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AD6673BCPZRL7-250 Datasheet(PDF) 4 Page - Analog Devices

No. de pieza AD6673BCPZRL7-250
Descripción Electrónicos  80 MHz Bandwidth, Dual IF Receiver
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
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AD6673BCPZRL7-250 Datasheet(HTML) 4 Page - Analog Devices

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AD6673
Data Sheet
Rev. C | Page 4 of 45
GENERAL DESCRIPTION
The AD6673 is an 11-bit, 250 MSPS, dual-channel intermediate
frequency (IF) receiver specifically designed to support multi-
antenna systems in telecommunication applications where high
dynamic range performance, low power, and small size are desired.
The device consists of two high performance analog-to-digital
converters (ADCs) and noise shaping requantizer (NSR) digital
blocks. Each ADC consists of a multistage, differential pipelined
architecture with integrated output error correction logic, and
each ADC features a wide bandwidth switched capacitor sampling
network within the first stage of the differential pipeline. An
integrated voltage reference eases design considerations. A duty
cycle stabilizer (DCS) compensates for variations in the ADC
clock duty cycle, allowing the converters to maintain excellent
performance.
Each ADC output is connected internally to an NSR block. The
integrated NSR circuitry allows for improved SNR performance
in a smaller frequency band within the Nyquist bandwidth. The
device supports two different output modes selectable via the
SPI. With the NSR feature enabled, the outputs of the ADCs
are processed such that the AD6673 supports enhanced SNR
performance within a limited portion of the Nyquist bandwidth
while maintaining an 11-bit output resolution.
The NSR block can be programmed to provide a bandwidth of
either 22% or 33% of the sample clock. For example, with a sample
clock rate of 250 MSPS, the AD6673 can achieve up to 76.3 dBFS
SNR for a 55 MHz bandwidth in the 22% mode and up to
73.5 dBFS SNR for a 82 MHz bandwidth in the 33% mode.
When the NSR block is disabled, the ADC data is provided directly
to the output at a resolution of 11 bits. The AD6673 can achieve
up to 65.9 dBFS SNR for the entire Nyquist bandwidth when
operated in this mode. This allows the AD6673 to be used in
telecommunication applications such as a digital predistortion
observation path where wider bandwidths are required.
By default, the ADC output data is routed directly to the two
external JESD204B serial output lanes. These outputs are at current
mode logic (CML) voltage levels. Two modes are supported such
that output coded data is either sent through one lane or two
(L = 1; F = 4 or L = 2; F = 2). Single lane operation supports
converter rates up to 125 MSPS. Synchronization input controls
(SYNCINB± and SYSREF±) are provided.
The AD6673 receiver digitizes a wide spectrum of IF frequencies.
Each receiver is designed for simultaneous reception of a separate
antenna. This IF sampling architecture greatly reduces component
cost and complexity compared with traditional analog techniques
or less integrated digital methods.
Flexible power-down options allow significant power savings,
when desired. Programmable overrange level detection is
supported for each channel via dedicated fast detect pins.
Programming for setup and control are accomplished using a
3-wire SPI-compatible serial interface with numerous modes to
support board level system testing.
The AD6673 is available in a 48-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C.


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