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93L00DMQB Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No. de pieza 93L00DMQB
Descripción Electrónicos  4-Bit Universal Shift Register
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Fabricante Electrónico  NSC [National Semiconductor (TI)]
Página de inicio  http://www.national.com
Logo NSC - National Semiconductor (TI)

93L00DMQB Datasheet(HTML) 4 Page - National Semiconductor (TI)

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Functional Description
The Logic Diagrams and Truth Table indicate the functional
characteristics of the 93L00 4-bit shift register The device is
useful in a wide variety of shifting counting and storage
applications It performs serial parallel serial-to-parallel or
parallel-to-serial data transfers
The 93L00 has two primary modes of operation shift right
(Q0
xQ1) and parallel load which are controlled by the
state of the Parallel Enable (PE) input When the PE input is
HIGH serial data enters the first flip-flop Q0 via the J and K
inputs
and
is
shifted
one
bit
in
the
direction
Q0
xQ1xQ2xQ3 following each LOW-to-HIGH
clock transition The JK inputs provide the flexibility of the
JK type input for special applications and the simple D-type
input for general applications by tying the two pins together
When the PE input is LOW the 93L00 appears as four com-
mon clocked D flip-flops The data on the parallel inputs
P0 – P3 is transferred to the respective Q0 – Q3 outputs fol-
lowing the LOW-to-HIGH clock transition Shift left opera-
tion (Q3
xQ2) can be achieved by tying the Qn outputs to
the Pnb1 inputs and holding the PE input LOW
All serial and parallel data transfers are synchronous occur-
ing after each LOW-to-HIGH clock transition Since the
93L00 utilizes edge triggering there is no restriction on the
activity of the J K Pn and PE inputs for logic operationex-
cept for the setup and release time requirements A LOW on
the asynchronous Master Reset (MR) input sets all Q out-
puts LOW independent of any other input condition
Truth Table
Operating
Inputs (MR e H)
Outputs
tna1
Mode
PE
JK
P0
P1
P2
P3
Q0
Q1
Q2
Q3
Q3
H
L
L
X
X
X
X
L
Q0
Q1
Q2
Q2
Shift Mode
H
L
H
X
X
X
X
Q0Q0Q1Q2Q2
H
H
L
XXXX
Q0Q0Q1Q2Q2
H
H
H
X
X
X
X
H
Q0
Q1
Q2
Q2
Parallel
L
X
X
L
L
L
L
L
L
L
L
H
Entry Mode
L
X
X
H
H
H
H
H
H
H
H
L
tna1 e Indicates state after next LOW-to-HIGH clock transition
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
4


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