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93L14DMQB Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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93L14DMQB Datasheet(HTML) 4 Page - National Semiconductor (TI) |
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4 / 6 page  Functional Description The 93L14 consists of four latches with a common active LOW Enable input and active LOW Master Reset input When the Enable goes HIGH data present in the latches is stored and the state of the latch is no longer affected by the Sn and Dn inputs The Master Reset when activated over- rides all other input conditions forcing all latch outputs LOW Each of the four latches can be operated in one of two modes D-TYPE-LATCHFor D-type operation the S input of a latch is held LOW While the common Enable is active the latch output follows the D input Information present at the latch output is stored in the latch when the Enable goes HIGH SETRESET LATCHDuring setreset operation when the common Enable is LOW a latch is reset by a LOW on the D input and can be set by a LOW on the S input if the D input is HIGH If both S and D inputs are LOW the D input will dominate and the latch wil be reset When the Enable goes HIGH the latch remains in the last state prior to disable- ment The two modes of latch operation are shown in the Truth Table Truth Table MR E DS Qn Operation H L L L L D Mode HL H L L HH X X Qnb1 H L L L L RS Mode HL H L H HL L H L H L HHQnb1 HH X X Qnb1 L X X X L RESET H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Qnb1 e Previous Output State Qn e Present Output State Logic Diagram TLF9612 – 3 4 |
Número de pieza similar - 93L14DMQB |
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Descripción similar - 93L14DMQB |
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