ADC08061BIN datasheet(2/16 Pages) NSC

No. de pieza	ADC08061BIN

Descripción Electrónicos	500 ns A/D Converter with S/H Function and Input Multiplexer

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Fabricante Electrónico	NSC [National Semiconductor (TI)]

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Connection Diagrams

Ordering Information

Industrial (−40˚C

≤ T

A ≤ 85˚C)

Package

ADC08061BIN, ADC08062BIN

N20A

ADC08061CIWM, ADC08062CIWM

M20B

Pin Description

V

IN,

V

IN1–8

These are analog inputs. The input range is

GND–50 mV

≤ V

INPUT

≤ V+ +50mV. The

ADC08061 has a single input (V

IN)

and the

ADC08062

has

a

two-channel

multiplexer

(V

IN1–2).

DB0–DB7 TRI-STATE data outputs — bit 0 (LSB) through

bit 7 (MSB).

WR /RDY

WR-RD Mode (Logic high applied to MODE pin)

WR: With CS low, the conversion is started on

the falling edge of WR. The digital result will be

strobed into the output latch at the end of con-

version (see

Figures 2, 3, 4).

:

RD Mode (Logic low applied to MODE pin)

RDY: This is an open drain output (no internal

pull-up device). RDY will go low after the falling

edge of CS and return high at the end of conver-

sion.

MODE

Mode:

Mode

(RD

or

WR-RD)

selection

input — This pin is pulled to a logic low through

an internal 50 µA current sink when left uncon-

nected.

RD Mode is selected if the MODE pin is left un-

connected or externally forced low. A complete

conversion is accomplished by pulling RD low

until output data appears.

WR-RD Mode is selected when a high is applied

to the MODE pin. A conversion starts with the

WR signal’s rising edge and then using RD to

access the data.

RD

WR-RD Mode (logic high on the MODE pin)

This is the active low Read input. With a logic

low applied to the CS pin, the TRI-STATE data

outputs (DB0–DB7) will be activated when RD

goes low (

Figures 2, 3, 4).

RD Mode (logic low on the MODE pin)

With CS low, a conversion starts on the falling

edge of RD. Output data appears on DB0–DB7

at the end of conversion(see

Figures 1, 5).

INT

This is an active low output that indicates that a

conversion is complete and the data is in the

output latch. INT is reset by the rising edge of

RD.

GND

This is the power supply ground pin. The ground

pin should be connected to a “clean” ground ref-

erence point.

V

REF−,

V

REF+

These are the reference voltage inputs. They

may be placed at any voltage between GND −

50 mV and V

+ +50mV, but V

REF+ must be

greater than V

REF−. Ideally, an input voltage

equal to V

REF− produces an output code of 0,

and an input voltage greater than V

REF+ − 1.5

LSB produces an output code of 255.

For the ADC08062, an input voltage on any un-

selected input that exceeds V

+ by more than

100 mV or is below GND by more than 100 mV

will create errors in a selected channel that is

operating within proper operating conditions.

CS

This is the active low Chip Select input. A logic

low signal applied to this input pin enables the

RD and WR inputs. Internally, the CS signal is

ORed with RD and WR signals.

OFL

Overflow Output. If the analog input is higher

than V

REF+ −

1

⁄2 LSB, OFL will be low at the end

of conversion. It can be used when cascading

two ADC08061s to achieve higher resolution (9

bits). This output is always active and does not

go into TRI-STATE as DB0–DB7 do. When OFL

is set, all data outputs remain high when the

ADC08061’s output data is read.

NC

No connection.

DS011086-14

Dual-In-Line and Wide-Body

Small-Outline

Packages N20A or M20B

DS011086-15

Dual-In-Line and Wide-Body

Small-Outline

Packages N20A or M20B

www.national.com

2

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