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TC90105FG Datasheet(PDF) 11 Page - Toshiba Semiconductor |
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TC90105FG Datasheet(HTML) 11 Page - Toshiba Semiconductor |
11 / 18 page Summary TC90105FG ©2015 TOSHIBA CORPORATION Page 11 Rev.1.00 2015/11/11 5.3.2 Multiplex processing output In a two CVBS input, multiplex processing can be carried out and two outputs can be outputted. Multiplex processing output becomes the same format from by two lines, although either of ITU-R BT.601 and ITU-R BT.656 of the formats is possible. When multiplex processing is performed, a clock output has 6.5.2.1 Type1 and the two modes of 6.5.2.2 Type2. Type1 : The mode which outputs the flag of the output of which system in addition to the clock which carried out multiplex. Type2 : The mode which outputs each clock. 5.3.2.1. Type1 It is the mode which outputs the data signal which acted as multiplex, the same clock signal of frequency, and the flag signal ofwhich system to output. At the time of default configuration, a flag signal serves as a high output at the time of the output of CoreA (Segment 0x01), and serves as a low output at the time of the output of CoreB (Segment 0x02). 5.3.2.2. Type2 It is the mode which outputs the clock of two outputs from another terminal, respectively. Since it acts as multiplex of the data signal, the clock signal in this mode is outputted on the frequency of the half of a data signal. CLK A A B A B A B CLK B DATA CLK A A B A B A B CLK B DATA |
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