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ADC0852CCN Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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ADC0852CCN Datasheet(HTML) 4 Page - National Semiconductor (TI) |
4 / 20 page AC Characteristics tr e tf e 20 ns TA e 25 C Typ Tested Design Symbol Parameter Conditions (Note 4) Limit Limit Units (Note 5) (Note 6) fCLK Clock Frequency MIN 10 kHz (Note 12) MAX 400 kHz tD1 Rising Edge of Clock CL e 100 pF 650 1000 ns to ‘‘DO’’ Enabled tr Comparator Response Not Including 2 a 1 ms 1fCLK Time (Note 13) Addressing Time Clock Duty Cycle MIN 40 % (Note 10) MAX 60 % tSET-UP CS Falling Edge or MAX 250 ns Data Input Valid to CLK Rising Edge tHOLD Data Input Valid after MIN 90 ns CLK Rising Edge tpd1 tpd0 CLK Falling Edge to MAX CL e 100 pF 650 1000 ns Output Data Valid (Note 11) t1H t0H Rising Edge of CS to MAX CL e 10 pF RL e 10k 125 250 ns Data Output Hi-Z CL e 100 pF RL e 2k 500 500 ns (see TRI-STATE Test Circuits) CIN Capacitance of Logic 5 pF Input COUT Capacitance of Logic 5 pF Outputs Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions Note 2 All voltages are measured with respect to ground Note 3 Internal zener diodes (approx 7V) are connected from Va to GND and VCC to GND The zener at Va can operate as a shunt regulator and is connected to VCC via a conventional diode Since the zener voltage equals the AD’s breakdown voltage the diode ensures that VCC will be below breakdown when the device is powered from Va Functionality is therefore guaranteed for Va operation even though the resultant voltage at VCC may exceed the specified Absolute Max of 65V It is recommended that a resistor be used to limit the max current into Va Note 4 Typicals are at 25 C and represent most likely parametric norm Note 5 Tested and guaranteed to National AOQL (Average Outgoing Quality Level) Note 6 Guaranteed but not 100% production tested These limits are not used to calculate outgoing quality levels Note 7 Total unadjusted error includes comparator offset DAC linearity and multiplexer error It is expressed in LSBs of the threshold DAC’s input code Note 8 For VIN(b)tVIN(a) the output will be 0 Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply Be careful during testing at low VCC levels (45V) as high level analog inputs (5V) can cause this input diode to conductespecially at elevated temperatures and cause errors for analog inputs near full-scale The spec allows 50 mV forward bias of either diode This means that as long as the analog VIN or VREF does not exceed the supply voltage by more than 50 mV the output code will be correct To achieve an absolute 0 VDC to5VDC input voltage range will therefore require a minimum supply voltage of 4950 VDC over temperature variations initial tolerance and loading Note 9 Leakage current is measured with the clock not switching Note 10 A 40% to 60% clock duty cycle range ensures proper operation at all clock frequencies In the case that an available clock has a duty cycle outside of these limits then 16 mS s CLK Low s 60 mS and 16 mS s CLK HIGH s % Note 11 With CS low and programming complete D0 is updated on each falling CLK edge However each new output is based on the comparison completed 05 clock cycles prior (see Figure 5 ) Note 12 Error specs are not guaranteed at 400 kHz (see graph Comparator Error vs fCLK) Note 13 See text section 12 Note 14 Human body model 100 pF discharged through a 15 kX resistor Note 15 Because the reference ladder of the ADC0852 is internally connected to VCC ladder resistance cannot be directly tested for the ADC0852 Ladder current is included in the ADC0852’s supply current specification 4 |
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