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ADC1173CIJM Datasheet(PDF) 10 Page - National Semiconductor (TI) |
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ADC1173CIJM Datasheet(HTML) 10 Page - National Semiconductor (TI) |
10 / 17 page Functional Description The ADC1173 uses a new, unique architecture to achieve 7.4 effective bits at and maintains superior dynamic perfor- mance up to 1⁄2 the clock frequency. The analog signal at V IN that is within the voltage range set by V RT and VRB are digitized to eight bits at up to 20 MSPS. Input voltages below V RB will cause the output word to con- sist of all zeroes. Input voltages above V RT will cause the output word to consist of all ones. V RT has a range of 1.0 Volt to the analog supply voltage, AV DD, while VRB has a range of 0 to 2.0 Volts. V RT should always be at least 1.0 Volt more positive than V RB. If V RT and VRTS are connected together and VRB and VRBS are connected together, the nominal values of V RT and VRB are 1.56V and 0.36V, respectively. If V RT and VRTS are con- nected together and V RB is grounded, the nominal value of V RT is 1.38V. Data is acquired at the falling edge of the clock and the digi- tal equivalent of the data is available at the digital outputs 2.5 clock cycles plus t OD later. The ADC1173 will convert as long as the clock signal is present at pin 12. The Output Enable pin OE, when low, enables the output pins. The digital out- puts are in the high impedance state when the OE pin is high. Applications Information 1.0 The Analog Input The analog input of the ADC1173 is a switch followed by an integrator. The input capacitance changes with the clock level, appearing as 4 pF when the clock is low, and 11 pF when the clock is high. Since a dynamic capacitance is more difficult to drive than a fixed capacitance, choose an amplifier that can drive this type of load. The CLC409, CLC440, LM6152, LM6154, LM6181 and LM6182 have been found to be excellent devices for driving the ADC1173. Do not drive the input beyond the supply rails. Figure 3 shows an example of an input circuit using the LM6181. This circuit has both gain and offset adjustments. If you desire to eliminate these adjustments, you should re- duce the signal swing to avoid clipping at the ADC1173 out- put that can result from normal tolerances of all system com- ponents. With no adjustments, the nominal value for the amplifier feedback resistor is 510 Ω and the 5.1k resistor at the inverting input should be changed to 860 Ω and returned to +3V rather than to the Offset Adjust potentiometer. 2.0 Reference Inputs The reference inputs V RT (Reference Top) and VRB (Refer- ence Bottom) are the top and bottom of the reference ladder. Input signals between these two voltages will be digitized to 8 bits. External voltages applied to the reference input pins should be within the range specified in the Operating Ratings table (1.0V to AV DD for VRT and 0V to (AVDD - 1.0V) for VRB). Any device used to drive the reference pins should be able to source sufficient current into the V RT pin and sink sufficient current from the V RB pin. The reference ladder can be self-biased by connecting V RT to V RTS and connecting VRB to VRBS to provide top and bot- tom reference voltages of approximately 1.56V and 0.36V, respectively, with V CC = 3.0V. This connection is shown in Figure 3.IfV RT and VRTS are tied together, but VRB is tied to analog ground, a top reference voltage of approximately 1.38V is generated. The top and bottom of the ladder should be bypassed with 10µF tantalum capacitors located close to the reference pins. The reference self-bias circuit of Figure 3 is very simple and performance is adequate for many applications. Superior performance can generally be achieved by driving the refer- ence pins with a low impedance source. By forcing a little current into or out of the top and bottom of the ladder, as shown in Figure 4, the top and bottom refer- ence voltages can be trimmed. The resistive divider at the amplifier inputs can be replaced with potentiometers. The LMC662 amplifier shown was chosen for its low offset volt- age and low cost. Note that a negative power supply is needed for these amplifiers as their outputs may be required to go slightly negative to force the required reference voltages. www.national.com 10 |
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