Pin Descriptions

PLCC and

Pin

SSOP Pkg.

Name

Description

Pin Number

5

6

V

V

The analog ADC inputs. V

input into the ADC.

10

V

Positive reference input. The operating voltage range for this input is 1V

≤ V

3 and Figure 4). This pin should be bypassed to AGND at least with a parallel combination of a 10

µF and a 0.1 µF (ceramic) capacitor. The capacitors should be placed as close to the part as

possible.

9V

Negative reference input. The operating voltage range for this input is 0V

≤ V

Figure 3 and Figure 4). This pin should be bypassed to AGND at least with a parallel combination of

a 10 µF and a 0.1 µF (ceramic) capacitor. The capacitors should be placed as close to the part as

possible.

4

WMODE

The logic state of this pin at power-up determines which edge of the write signal (WR ) will latch in

data from the data bus. If tied low, the ADC12041 will latch in data on the rising edge of the WR

signal. If tied to a logic high, data will be latched in on the falling edge of the WR signal. The state of

this pin should not be changed after power-up.

27

SYNC

The SYNC pin can be programmed as an input or an output. The Configuration register’s bit b4

controls the function of this pin. When programmed as an input pin (b4 = 1), a rising edge on this

pin causes the ADC’s sample-and-hold to hold the analog input signal and begin conversion. When

programmed as an output pin (b4 = 0), the SYNC pin goes high when a conversion begins and

returns low when completed.

12–20

23–26

D0–D8

D9–D12

13-bit Data bus of the ADC12041. D12 is the most significant bit and D0 is the least significant. The

BW(bus width) bit of the Configuration register (b3) selects between an 8-bit or 13-bit data bus width.

When the BW bit is set (BW = 1), D12–D0 are active.

28

CLK

The clock input pin used to drive the ADC12041. The operating range is 0.05 MHz to 12 MHz.

1WR

WR is the active low WRITE control input pin. A logic low on this pin and the CS will enable the

input buffers of the data pins D12–D0. The signal at this pin is used by the ADC12041 to latch in

data on D12–D0. The sense of the WMODE pin at power-up will determine which edge of the WR

signal the ADC12041 will latch in data. See WMODE pin description.

2RD

RD is the active low read control input pin. A logic low on this pin and CS will enable the active

output buffers to drive the data bus.

3CS

CS is the active low Chip Select input pin. Used in conjunction with the WR and RD signals to

control the active data bus input/output buffers of the data bus.

11

RDY

RDY is an active low output pin. The signal at this pin indicates when a requested function has

begun or ended. Refer to section Functional Description and the digital timing diagrams for more

detail.

7V

guaranteed only if the V

bypassed to AGND with a parallel combination of a 10 µF and a 0.1 µF (ceramic) capacitor. The

capacitors should be placed as close to the supply pins of the part as possible.

8

AGND

Analog ground pin. This is the device’s analog supply ground connection. It should be connected

through a low resistance and low inductance ground return to the system power supply.

21

V

guaranteed only if the V

bypassed to DGND with a parallel combination of a 10 µF and a 0.1 µF (ceramic) capacitor. The

capacitors should be placed as close to the supply pins of the part as possible.

22

DGND

Digital ground pin. This is the device’s digital supply ground connection. It should be connected

through a low resistance and low inductance ground return to the system power supply.

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