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TDC7200PW Datasheet(PDF) 7 Page - Texas Instruments |
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TDC7200PW Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 50 page  7 TDC7200 www.ti.com SNAS647D – FEBRUARY 2015 – REVISED MARCH 2016 Product Folder Links: TDC7200 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated (1) Accuracy is defined as the systematic error in the output signal; the error of the device excluding noise. (2) Specified by design. 7.5 Electrical Characteristics TA = 25°C , VDD = 3.3 V, GND = 0 V (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TDC CHARACTERISTICS LSB Resolution Single shot measurement 55 ps TACC-2 Accuracy (Mode 2) (1) CLOCK = 8 MHz 28 ps TSTD-2 Standard Deviation (Mode 2) Measured time = 100 µs 50 ps Measured time = 1 µs 35 ps OUTPUT CHARACTERISTICS: TRIGG, INTB, DOUT VOH Output voltage high Isource = -2 mA 2.31 2.95 V VOL Output voltage low Isink = 2 mA 0.35 0.99 V INPUT CHARACTERISTICS: ENABLE, START, STOP, CLOCK, DIN, CSB,SCLK Cin Input capacitance (2) 3 pF POWER CONSUMPTION (see Measurement Mode 1 and Measurement Mode 2) Ish Shutdown current EN = LOW 0.3 2 µA IQA Quiescent Current A EN = HIGH; TDC running 1.35 mA IQB Quiescent Current B EN = HIGH; TDC OFF, Clock Counter running 71 µA IQC Quiescent Current C EN = HIGH; measurement stopped, SPI communication only 87 µA IQD Quiescent Current D EN = HIGH, TDC OFF, counter stopped, no communication 50 µA 7.6 Timing Requirements MIN NOM MAX UNIT TIMING REQUIREMENTS: START, STOP INPUTS, CLOCK PWSTART Pulse width for Start Signal 10 ns PWSTOP Pulse width for Stop Signal 10 ns SERIAL INTERFACE TIMING CHARACTERISTICS (VDD = 3.3 V, fSCLK = 20 MHz) (See Figure 1) fSCLK SCLK Frequency 20 MHz t1 SCLK period 50 ns t2 SCLK High Time 16 ns t3 SCLK Low Time 16 ns t4 DIN setup time 4 ns t5 DIN hold time 4 ns t6 CSB fall to SCLK rise 6 ns t7 Last SCLK rising edge to CSB rising edge 6 ns t8 Minimum pause time (CSB high) 40 ns t9 Clk fall to DOUT bus transition 12 ns 7.7 Switching Characteristics TA = 25°C , VDD = 3.3 V, GND = 0 V (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT WAKE UP TIME TWAKEUP_PERIOD Time to be ready for Measurement LSB within 0.3% of settled value 300 µs |
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